ZHCSFL8C October 2016 – August 2021 TPS65983B
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SPI | ||||||
SPI_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
SPI_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
SPI_HYS | Input hysteresis voltage | LDO_3V3 = 3.3 V | 0.2 | V | ||
SPI_ILKG | Leakage current | Output is Hi-Z, VIN = 0 to LDO_3V3 | –1 | 1 | μA | |
SPI_VOH | SPI output high voltage | IO = –8 mA, LDO_3V3=3.3 V | 2.9 | V | ||
IO = –15 mA, LDO_3V3=3.3 V | 2.5 | |||||
SPI_VOL | SPI output low voltage | IO = 10 mA | 0.4 | V | ||
IO = 20 mA | 0.8 | |||||
SWDIO | ||||||
SWDIO_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
SWDIO_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
SWDIO_HYS | Input Hysteresis Voltage | LDO_3V3 = 3.3 V | 0.2 | V | ||
SWDIO_ILKG | Leakage current | Output is Hi-Z, VIN = 0 to LDO_3V3 | –1 | 1 | μA | |
SWDIO_VOH | Output high voltage | IO = –8 mA, LDO_3V3 = 3.3 V | 2.9 | V | ||
IO = –15 mA, LDO_3V3 = 3.3 V | 2.5 | |||||
SWDIO_VOL | Output low voltage | IO = 10 mA | 0.4 | V | ||
IO = 20 mA | 0.8 | |||||
SWDIO_RPU | Pullup resistance | 2.8 | 4 | 5.2 | kΩ | |
SWDIO_TOS | SWDIO output skew to falling edge SWDCLK | –5 | 5 | ns | ||
SWDIO_TIS | Input setup time required between SWDIO and rising edge of SWCLK | 6 | ns | |||
SWDIO_TIH | Input hold time required between SWDIO and rising edge of SWCLK | 1 | ns | |||
SWDCLK | ||||||
SWDCL_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
SWDCL_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
SWDCL_THI | SWDIOCLK HIGH period | 0.05 | 500 | μs | ||
SWDCL_TLO | SWDIOCLK LOW period | 0.05 | 500 | μs | ||
SWDCL_HYS | Input hysteresis voltage | LDO_3V3 = 3.3 V | 0.2 | V | ||
SWDCL_RPU | Pullup resistance | 2.8 | 4 | 5.2 | kΩ | |
GPIO, MRESET, RESETZ, BUSPOWERZ | ||||||
GPIO_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
VDDIO = 1.8 V | 1.25 | |||||
GPIO_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
VDDIO = 1.8 V | 0.63 | |||||
GPIO_HYS | Input hysteresis Voltage | LDO_3V3 = 3.3 V | 0.2 | V | ||
VDDIO = 1.8 V | 0.09 | |||||
GPIO_ILKG | I/O leakage current | INPUT = 0 V to VDD | –1 | 1 | μA | |
GPIO_RPU | Pullup resistance | Pullup enabled | 50 | 100 | 150 | kΩ |
DEBUG_CRTL1/2 pullup resistance | Pullup enabled | 2.5 | 5 | 7.5 | kΩ | |
GPIO_RPD | Pulldown resistance (DEBUG_CRTL1/2 have no pulldown resistance path) | Pulldown enabled | 50 | 100 | 150 | kΩ |
GPIO_DG | Digital input path deglitch | 20 | ns | |||
GPIO_VOH | GPIO output high voltage | IO = –2 mA, LDO_3V3 = 3.3 V | 2.9 | V | ||
IO = –2 mA, VDDIO = 1.8 V | 1.35 | |||||
GPIO_VOL | GPIO output low voltage | IO = 2 mA, LDO_3V3 = 3.3 V | 0.4 | V | ||
IO = 2 mA, VDDIO = 1.8 V | 0.45 | |||||
HRESET | ||||||
HRESET_VIH | High-level input voltage | 1.25 | V | |||
HRESET_VIL | Low-level input voltage | 0.63 | V | |||
HRESET_HYS | Input hysteresis Voltage | .09 | V | |||
HRESET_ILKG | I/O leakage current | INPUT = 0 V to LDO_1V8D | –1 | 1 | μA | |
HRESET_THIGH | HRESET minimum high time to assert a reset condition. | 2.0 | ms | |||
HRESET_TLOW | HRESET minimum low time to deassert a reset condition. | 2.0 | ||||
UART_RX/TX, LSX_P2R/R2P | ||||||
UARTRX_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
VDDDIO = 1.8 V | 1.25 | |||||
UARTRX_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
VDDIO = 1.8 V | 0.63 | |||||
UARTRX_HYS | Input hysteresis voltage | LDO_3V3 = 3.3 V | 0.2 | V | ||
VDDIO = 1.8 V | 0.09 | |||||
UARTTX_VOH | GPIO output high voltage | IO = –2 mA, LDO_3V3 = 3.3 V | 2.9 | V | ||
IO = –2 mA, VDDIO = 1.8 V | 1.35 | |||||
UARTTX_VOL | GPIO output low voltage | IO = 2 mA, LDO_3V3 = 3.3 V | 0.4 | V | ||
IO = 2 mA, VDDIO = 1.8 V | 0.45 | |||||
UARTTX_RO | Output impedance, TX channel | LDO_3V3 = 3.3 V | 35 | 70 | 115 | Ω |
UARTTX_TRTF | Rise and fall time, TX channel | 10%–90%, CL = 20 pF | 1 | 40 | ns | |
UART_FMAX | Maximum UART baud rate | 1.1 | Mbps | |||
I2C_IRQ1Z, I2C_IRQ2Z | ||||||
OD_VOL | Low level output voltage | IOL = 2 mA | 0.4 | V | ||
OD_LKG | Leakage current | Output is Hi-Z, VIN = 0 to LDO_3V3 | –1 | 1 | μA | |
SBU | ||||||
SBU_VIH | High-level input voltage | LDO_3V3 = 3.3 V | 2 | V | ||
SBU_VIL | Low-level input voltage | LDO_3V3 = 3.3 V | 0.8 | V | ||
SBU_HYS | Input hysteresis voltage | LDO_3V3 = 3.3 V | 0.2 | V |