The TPS65987DDJ loads any ROM patch and-or configuration from flash memory during the boot sequence. The TPS65987DDJ is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 64 kB. The SPI controller of the TPS65987DDJ supports SPI Mode 0. For Mode 0, data delay is defined s0 that data is output on the same cycle as chip select (SPI_CS pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_POCI and SPI_PICO pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 KB. The W25X05CL or similar is recommended.