The TPS65987DDJ and the Thunderbolt controller share the same flash and they must be able to access it at different times. The TPS65987DDJ will access the flash first to load its configuration and then the Thunderbolt controller will read the flash for its firmware. The TPS65987DDJ will hold the Thunderbolt controller in reset until it has read its configuration from the flash. GPIO_0 is reserved to act as the reset signal for the Thunderbolt controller. The RESET_N (Thunderbolt Controller Master Reset) signal must also be gated by the 3.3-V supply to the Thunderbolt controller (VCC3P3_SX). When the RESET_N signal is de-asserted before the supply has come up it may put the Thunderbolt controller in a latched state. The RESET_N signal must be de-asserted at least 100 µs after the Thunderbolt Controller supply has come up. For dead battery operation the GPIO_0 signal should be “ANDed” with the 3.3-V supply to avoid de-asserting the RESETN when the Thunderbolt controller is not powered. The figure below shows the RESET_N control with GPIO_0 and the 3.3-V supply. Alternatively, the EC could configure GPIO_0 to de-assert RESETN when the system has successfully booted.

Figure 9-8 RESETN Circuit