Top and bottom placement is used for this example to minimize solution size. The TPS65987DDK is placed on the top side of the board and the majority of its components are placed on the bottom side. When placing the components on the bottom side, it is recommended that they are placed directly under the TPS65987DDK. When placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to face outward from the TPS65987DDK or to the side since the drain connection pads on the bottom layer should not be connected to anything and left floating. All other components that are for pins on the GND pad side of the TPS65987DDK should be placed where the GND terminal is underneath the GND pad.

The CC capacitors must be placed on the same side as the TPS65987DDK close to the respective CC1 and CC2 pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC capacitor is recommended.

The ADCIN1/2 voltage divider resistors can be placed where convenient. In this layout example they are placed on the opposite layer of the TPS65987DDK close to the LDO_3V3 pin to simplify routing.

The figures below show the placement in 2-D and 3-D.

Figure 11-3 Top View Layout

Figure 11-5 Top View 3-D

Figure 11-4 Bottom View Layout

Figure 11-6 Bottom View 3-D