On the top side, create pours for PP_HV1/2 and VBUS1/2 to extend area to place 8-mil hole and 16-mil diameter vias to connect to the bottom layer. See the figure below for the recommended via sizing.

Figure 11-7 Recommended Minimum Via Sizing

A minimum of four vias should be used to connect between the top and bottom layer power paths. For the bottom layer, place pours that will connect the PP_HV1/2 and VBUS capacitors to their respective vias. For 5-A systems, special consideration must be taken for ensuring enough copper is used to handle the higher current. For 0.5-oz copper, top or bottom pours, with 0.5-oz plating will require about 120-mil pour width for 5-A support. When routing the 5 A through a 0.5-oz internal layer, more than 200 mil will be required to carry the current.

The figures below show the pours used in this example.

Figure 11-8 Top Polygon Pours

Figure 11-9 Bottom Polygon Pours

For PP_CABLE, it is recommended to connect the capacitor to the pin with two vias. They should be placed side by side and as close to the pin as possible to allow for routing the CC lines.

Connect the bottom side VIN_3V3 and LDO_3V3 capacitors with traces through a via. The vias should have a straight connection to the respective pins. LDO_1V8 is connected through a via on the outside of the pin and connected with a trace on the bottom side capacitor.