ZHCSIY2B July 2018 – August 2021 TPS65988
PRODUCTION DATA
Each of the TPS65988's two I2C slave interfaces responds to two unique I2C addresses. The first address allows communication with Port 1 of the TPS65988 and the second address allows communication with Port 2 of the TPS65988.
The boot flow sets the hardware configurable unique I2C addresses of the TPS65988 before the port s are enabled to respond to I2C transactions. For the I2C1 interface, the unique I2C address es are determined by the analog level set by the analog ADCIN2 pin (three bits) as shown in Table 8-2 and Table 8-3.
| DEFAULT I2C UNIQUE ADDRESS | |||||||
|---|---|---|---|---|---|---|---|
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0 | 1 | 0 | 0 | I2C_ADDR_DECODE_C1[2:0] | R/W | ||
| Note 1: Any bit is maskable for each port independently providing firmware override of the I2C address. | |||||||
| DEFAULT I2C UNIQUE ADDRESS | |||||||
|---|---|---|---|---|---|---|---|
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0 | 1 | 0 | 0 | I2C_ADDR_DECODE_C2[2:0] | R/W | ||
| Note 1: Any bit is maskable for each port independently providing firmware override of the I2C address. | |||||||
For the I2C2 interface, the unique I2C address is a fixed value as shown in Table 8-4 and Table 8-5.
| DEFAULT I2C UNIQUE ADDRESS | |||||||
|---|---|---|---|---|---|---|---|
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | R/W |
| Note 1: Any bit is maskable for each port independently, providing firmware override of the I2C address. | |||||||
| DEFAULT I2C UNIQUE ADDRESS | |||||||
|---|---|---|---|---|---|---|---|
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | R/W |
| Note 1: Any bit is maskable for each port independently, providing firmware override of the I2C address. | |||||||
The TPS65988 I2C address values are set and controlled by device firmware. Certain firmware configurations may override the presented address settings.