10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side, copper surface area. The use of vias and long traces to create LDO component connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.

10.2 Layout Example

1. Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal conduction.

Figure 37. Fixed Voltage Layout

1. Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal conduction.

Figure 38. Adjustable Voltage Layout

10.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (P_D) is equal to the product of the output current times the voltage drop across the output pass element (V_IN to V_OUT), as shown in Equation 4:

Equation 4.

A better method of estimating the thermal measure comes from using the thermal metrics Ψ_JT and Ψ_JB, shown in Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than R_θJA. The junction temperature can be estimated with Equation 5.

Equation 5.

where

• P_D is the power dissipation shown by Equation 4,
• T_T is the temperature at the center-top of the IC package,
• T_B is the PCB temperature measured 1 mm away from the IC package on the PCB surface.

For more information about measuring T_T and T_B, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com.