ZHCSEN1A February   2016  – October 2016 TPS720-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Inrush Current Limit
      3. 7.3.3 Shutdown
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Requirements
      2. 8.1.2 Output Regulation With the IN Pin Floating
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Transient Response
      5. 8.1.5 Minimum Load
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

at TJ = –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND(1)
MIN MAX UNIT
VIN(2) Input voltage (steady-state) –0.3 VBIAS or 5(3) V
VIN_PEAK(4) Peak transient input 5.5 V
VBIAS Bias voltage –0.3 6 V
VEN Enable voltage –0.3 6 V
VOUT Output voltage –0.3 5 V
IOUT Peak output current Internally limited
Output short-circuit duration Indefinite
PDISS Total continuous power dissipation See Thermal Information
TJ Operating junction temperature –55 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) To ensure proper device operation, VIN must be less than or equal to VBIAS under all conditions.
(3) Whichever is less.
(4) For durations no longer than 1 ms each, for a total of no more than 1000 occurrences over the lifetime of the device.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
Machine model (MM) ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VIN Input voltage (steady-state) 1.1 VBIAS or 4.5(1) V
VBIAS Bias voltage 2.6 or VOUT + 1.4(2) 5.5 V
VOUT Output voltage 0.9 3.6 V
IOUT Peak output current 0 350 mA
VEN Enable voltage 0 5.5 V
CIN Input capacitance 1 µF
CBIAS Bias capacitance 0.1 µF
COUT(3) Output capacitance 2.2 µF
(1) Whichever is less.
(2) Whichever is greater.
(3) Maximum ESR must be less than 250 mΩ.

6.4 Thermal Information

THERMAL METRIC(1) TPS720-Q1 UNIT
DRV (WSON)
6 PINS
RθJA Junction-to-ambient thermal resistance 66.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 86.2 °C/W
RθJB Junction-to-board thermal resistance 36.1 °C/W
ψJT Junction-to-top characterization parameter 1.7 °C/W
ψJB Junction-to-board characterization parameter 36.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

6.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V ) or 2.6 V (whichever is greater), VIN ≥ VOUT + 0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 1.1(1) VBIAS or 4.5(2) V
VBIAS Bias voltage 2.6 5.5 V
VOUT(4) Output voltage(3) 0.9 3.6 V
Output accuracy Over VBIAS, VIN, IOUT, TJ = –40°C to +125°C VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA		 –2% 2%
Over VBIAS, VIN, IOUT, TJ = –40°C to +125°C VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
VOUT + 0.5 V ≤ VIN ≤ 4.5 V,
0 mA ≤ IOUT ≤ 350 mA, VOUT < 1.2 V		 –25 25 mV
VIN floating VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V,
0 μA ≤ IOUT ≤ 500 μA		 ±1%
ΔVOUT/ΔVIN VIN line regulation VIN = (VOUT + 0.5 V) to 4.5 V, IOUT = 1 mA 16 μV/V
ΔVOUT/ΔVBIAS VBIAS line regulation VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater) to 5.5 V, IOUT = 1 mA 16 μV/V
VIN line transient ΔVIN = 400 mV, tRISE = tFALL = 1 μs ±200 μV
VBIAS line transient ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs ±0.8 mV
ΔVOUT/ΔIOUT Load regulation 0 mA ≤ IOUT ≤ 350 mA (no load to full load) –15 μV/mA
Load transient 0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs ±15 mV
VDO_IN VIN dropout voltage(5) VIN = VOUT(NOM) – 0.1 V,
(VBIAS – VOUT(NOM)) = 1.4 V,
IOUT = 350 mA		 110 200 mV
VDO_BIAS VBIAS dropout voltage(6) VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA 1.09 1.4 V
ICL Output current limit VOUT = 0.9 × VOUT(NOM) 420 600 800 mA
IGND Ground pin current IOUT = 100 μA 38 μA
IOUT = 0 mA to 350 mA 54 80
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V 0.5 2.5 μA
PSRR VIN power-supply rejection ratio VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA		 f = 10 Hz 85 dB
f = 100 Hz 85
f = 1 kHz 85
f = 10 kHz 80
f = 100 kHz 70
f = 1 MHz 50
PSRR VBIAS power-supply rejection ratio VIN – VOUT ≥ 0.5 V,
VBIAS = VOUT + 1.4 V,
IOUT = 350 mA		 f = 10 Hz 80 dB
f = 100 Hz 80
f = 1 kHz 75
f = 10 kHz 65
f = 100 kHz 55
f = 1 MHz 35
VN Output noise voltage Bandwidth = 10 Hz to 100 kHz, VBIAS ≥ 2.6 V,
VIN = VOUT + 0.5 V		 48 μVRMS
IVIN_INRUSH Inrush current on VIN VBIAS = (VOUT +1.4 V) or 2.6 V (whichever is greater), VIN = VOUT + 0.5 V 100 + ILOAD mA
VEN(HI) Enable pin high (enabled) 1.1 V
VEN(LO) Enable pin low (disabled) 0 0.4 V
IEN Enable pin current VEN = 5.5 V, VIN = 4.5 V, VBIAS = 5.5 V 1 µA
UVLO Undervoltage lockout VBIAS rising 2.35 2.45 2.59 V
UVLO hysteresis VBIAS falling 150 mV
TSD Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
TJ Operating junction temperature –40 125 °C
(1) Performance specifications are ensured to a minimum VIN = VOUT + 0.5 V.
(2) Whichever is less.
(3) VO nominal value is factory programmable through the on-chip EEPROM.
(4) Minimum VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater) and VIN = VOUT + 0.5 V.
(5) Measured for devices with VOUT(NOM) ≥ 1.2 V.
(6) VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1 V. Measured for devices with VOUT(NOM) ≥ 1.8 V.

6.6 Timing Requirements

MIN NOM MAX UNIT
tSTR Start-up time VOUT = 95%, VOUT (NOM), IOUT = 350 mA, COUT = 2.2 μF 140 µs

6.7 Typical Characteristics

over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4 V) or 2.6 V (whichever is greater), VIN = VOUT + 0.5 V, IOUT = 1 mA, VEN = 1.1 V, and COUT = 2.2 μF (unless otherwise noted); typical values are at TJ = 25°C
TPS720-Q1 D003_SBVS278.gif
IOUT = 0 mA
Figure 1. VIN Line Regulation (No Load)
TPS720-Q1 D005_SBVS278.gif
IOUT = 0 mA
Figure 3. VBIAS Line Regulation (No Load)
TPS720-Q1 D007_SBVS278.gif
Figure 5. Load Regulation Under Light Loads
TPS720-Q1 D001_SBVS278.gif
Figure 7. Load Regulation With VIN Floating
TPS720-Q1 tc_vdo-iout_sbvs278.gif
Figure 9. VIN Dropout Voltage vs Output Current
TPS720-Q1 D009_SBVS278.gif
Figure 11. Output Voltage vs Junction Temperature
TPS720-Q1 tc_ignd-iout_sbvs278.gif
Figure 13. Ground Pin Current vs Output Current
TPS720-Q1 tc_ishdn-vbias_sbvs278.gif
Figure 15. Shutdown Current vs VBIAS Voltage
TPS720-Q1 tc_icl-vin_sbvs278.gif
Figure 17. Current Limit vs Input Voltage
TPS720-Q1 tc_psrr-frq_iout_sbvs278.gif
IOUT = 350 mA
Figure 19. VIN Power-Supply Rejection Ratio vs Frequency
TPS720-Q1 tc_noise-frq_bvs100.gif
Figure 21. Output Spectral Noise Density vs Frequency
TPS720-Q1 tc_line_resp_vbias_sbvs278.gif
VIN = 2.3 V VOUT = 1.8 V VBIAS = 3.2 V to 3.8 V
VBIAS slew rate = 600 m/μs IOUT = 350 mA
Figure 23. VBIAS Line Transient Response
TPS720-Q1 D004_SBVS278.gif
IOUT = 350 mA
Figure 2. VIN Line Regulation (350 mA)
TPS720-Q1 D006_SBVS278.gif
IOUT = 350 mA
Figure 4. VBIAS Line Regulation (350 mA)
TPS720-Q1 D008_SBVS278.gif
Figure 6. Load Regulation
TPS720-Q1 D002_SBVS278.gif
VBIAS = 3.2 V
Figure 8. Load Regulation With VIN Floating
TPS720-Q1 tc_vdo-tmp_sbvs278.gif
VOUT = VOUT(NOM) – 0.1 V IOUT = 350 mA
Figure 10. VBIAS Dropout Voltage vs Junction Temperature
TPS720-Q1 tc_ignd-vbias_sbvs278.gif
IOUT = 1 mA
Figure 12. Ground Pin Current vs VBIAS Voltage
TPS720-Q1 tc_ignd-tmp_sbvs278.gif
IOUT = 350 mA
Figure 14. Ground Pin Current vs Junction Temperature
TPS720-Q1 tc_icl-vbias_sbvs278.gif
Figure 16. Current Limit vs VBIAS Voltage
TPS720-Q1 tc_psrr-frq_vin_sbvs278.gif
VIN – VOUT = 0.5 V, VBIAS – VOUT = 1.4 V
Figure 18. VIN Power-Supply Rejection Ratio vs Frequency
TPS720-Q1 tc_psrr-frq_vbias_sbvs278.gif
VIN – VOUT = 0.5 V VBIAS – VOUT = 1.4 V
Figure 20. VBIAS Power-Supply Rejection Ratio vs Frequency
TPS720-Q1 tc_line_resp_vin_sbvs278.gif
VIN = 2.1 to 2.5 V VOUT = 1.8 V VBIAS = 3.2 V
VIN slew rate = 1 V/μs IOUT = 350 mA
Figure 22. VIN Line Transient Response
TPS720-Q1 tc_load_resp_sbvs278.gif
VIN = 2.3 V VOUT = 1.8 V VBIAS = 3.2 V
tRISE = 1 μs
Figure 24. Load Transient Response
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