5.4 Thermal Information
| THERMAL METRIC(1) |
TPS735 (2) |
UNIT |
| DRB (SON) |
DRV (WSON) |
| 8 PINS |
6 PINS |
| RθJA |
Junction-to-ambient thermal resistance (3) |
52.2 |
65.1 |
°C/W |
| RθJC(top) |
Junction-to-case (top) thermal resistance (4) |
59.4 |
85.6 |
°C/W |
| RθJB |
Junction-to-board thermal resistance |
19.3 |
34.7 |
°C/W |
| ψJT |
Junction-to-top characterization parameter (5) |
2 |
1.6 |
°C/W |
| ψJB |
Junction-to-board characterization parameter (6) |
19.3 |
35.1 |
°C/W |
| RθJC(bot) |
Junction-to-case (bottom) thermal resistance (7) |
11.8 |
5.8 |
°C/W |
(2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
- i. DRB: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array.
ii. DRV: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array. Due to size limitation of thermal pad, 0.8-mm pitch array is used which is off the JEDEC standard.
- i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
ii DRV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
- These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-in × 3-in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.