| THERMAL METRIC(1)(2) |
TPS736 Legacy silicon(3) |
UNIT |
| DRB (VSON) |
DCQ (SOT-223) |
DBV (SOT-23) |
| 8 PINS |
6 PINS |
5 PINS |
| RθJA |
Junction-to-ambient thermal resistance(4) |
52.8 |
118.7 |
221.9 |
°C/W |
| RθJC(top) |
Junction-to-case (top) thermal resistance(5) |
60.4 |
64.9 |
74.9 |
°C/W |
| RθJB |
Junction-to-board thermal resistance(6) |
28.4 |
65.0 |
51.9 |
°C/W |
| ψJT |
Junction-to-top characterization parameter(7) |
2.1 |
14.0 |
2.8 |
°C/W |
| ψJB |
Junction-to-board characterization parameter(8) |
28.6 |
63.8 |
51.1 |
°C/W |
| RθJC(bot) |
Junction-to-case (bottom) thermal resistance(9) |
12.0 |
N/A |
N/A |
°C/W |
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.