ZHCSN49N January   2007  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable/Shutdown
      2. 6.3.2 Power Good
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjusting the Output Voltage
      2. 7.1.2 Input, Output, and Bias Capacitor Requirements
      3. 7.1.3 Transient Response
      4. 7.1.4 Dropout Voltage
      5. 7.1.5 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 Evaluation Modules
        2. 8.1.2.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.2.2.1 Design Requirements

The application powers the I/O rails of an FPGA, at VOUT(nom) = 1.5 V and IOUT(max) = 1.5 A. The only available rail is 3.3 V. The I/O pins are driven for only short durations with a 5% duty cycle, so thermal issues are not a concern.
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