Figure 8-7 is based off of a JESD51-7 four-layer high-K board. The allowable power dissipation was estimated using the following equation. As disscussed in the An empirical analysis of the impact of board layout on LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the allowable thermal dissipation can be improved by up to 50%.

Equation 8.

Figure 8-7 Allowable Power Dissipation