The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers and microprocessors); these capacitively coupled signals may produce undesirable output voltage transients. In these cases, TI recommends using a fixed-voltage version of the device, or isolating the FB node by placing a copper ground plane on the layer directly underneath the LDO circuitry and FB pin to minimize any undesirable signal coupling.

4-layer PCB

Figure 10-1 Junction-to-Ambient Thermal Resistance (R_θJA) vs PCB Copper Area (DRB Package)

4-layer PCB

Figure 10-3 Junction-to-Board Characterization Parameter (ψ_JB) vs PCB Copper Area (DRB Package)

Figure 10-5 Junction-to-Ambient Thermal Resistance (R_θJA) vs PCB Copper Area (KVU Package)

2-layer PCB

Figure 10-2 Junction-to-Ambient Thermal Resistance (R_θJA) vs PCB Copper Area (DRB Package)

2-layer PCB

Figure 10-4 Junction-to-Board Characterization Parameter (ψ_JB) vs PCB Copper Area (DRB Package)

Figure 10-6 Junction-to-Board Characterization Parameter (ψ_JB) vs PCB Copper Area (KVU Package)