SLVS351P September   2002  – March 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown
      2. 7.3.2 Start-Up
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Regulator Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Output Noise
        3. 8.2.2.3 Dropout Voltage
        4. 8.2.2.4 Programming the TPS79601 Adjustable LDO Regulator
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
      2. 10.1.2 Regulator Mounting
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
    4. 10.4 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage IN –0.3 6 V
EN –0.3 VIN + 0.3
OUT 6
Current Peak output Internally limited
Power dissipation Continuous total See Thermal Information
Temperature Junction, TJ –40 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2.7 5.5 V
IOUT Output current 0 1 A
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS796xx(3) UNIT
DRB (VSON) DCQ
(SOT-223)		 KTT (TO-263)
8 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 47.8 70.4 25 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 83 70 35
RθJB Junction-to-board thermal resistance N/A N/A N/A
ψJT Junction-to-top characterization parameter 2.1 6.8 1.5
ψJB Junction-to-board characterization parameter 17.8 30.1 8.52
RθJC(bot) Junction-to-case (bottom) thermal resistance 12.1 6.3 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.        
    ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array.        
    iii. KTT: The exposed pad is connected to the PCB ground layer through a 5 × 4 thermal via array.      
  2. i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.    
    ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.        
    iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
  3. These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see Power Dissipation and Estimating Junction Temperature.

6.5 Electrical Characteristics

Over recommended operating temperature range (TJ = –40°C to 125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA, COUT = 10 μF, and CNR = 0.01 μF, unless otherwise noted. Typical values are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage(1) 2.7 5.5 V
VFB Internal reference (TPS79601) 1.2 1.225 1.25 V
IOUT Continuous output current 0 1 A
VOUT Output voltage range TPS79601 1.225 5.5 – VDO V
Accuracy TPS79601(2) 0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V(1) 0.98VOUT(nom) VOUT(nom) 1.02VOUT(nom) V
Fixed VOUT < 5 V 0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V(1) –2% 2%
Fixed VOUT = 5 V 0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V(1) –3% 3%
ΔVO(ΔVI) Line regulation(1) VOUT + 1 V ≤ VIN ≤ 5.5 V 0.05 0.12 %/V
ΔVO(ΔIO) Load regulation 0 μA ≤ IOUT ≤ 1 A 5 mV
VDO Dropout voltage(3)
(VIN = VOUT(nom) – 0.1 V)		 TPS79628 IOUT = 1 A 270 365 mV
TPS79628DRB IOUT = 250 mA 52 90
TPS79630 IOUT = 1 A 250 345
TPS79633 IOUT = 1 A 220 325
TPS79650 IOUT = 1 A 200 300
ICL Output current limit VOUT = 0 V 2.4 4.2 A
IGND Ground pin current 0 μA ≤ IOUT ≤ 1 A 265 385 μA
ISHDN Shutdown current(4) VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V 0.07 1 μA
IFB Feedback pin current VFB = 1.225 V 1 µA
PSRR Power-supply rejection ratio (TPS79630) f = 100 Hz. IOUT = 10 mA 59 dB
f = 100 Hz, IOUT = 1 A 54
f = 10 kHz, IOUT = 1A 53
f = 100 kHz, IOUT = 1 A 42
Vn Output noise voltage (TPS79630) BW = 100 Hz to 100 kHz, IOUT = 1 A CNR = 0.001 μF 54 μVRMS
CNR = 0.0047 μF 46
CNR = 0.01 μF 41
CNR = 0.1 μF 40
Start-up time (TPS79630) RL = 3 Ω,
COUT = 1 μF		 CNR = 0.001 μF 50 μs
CNR = 0.0047 μF 75
CNR = 0.01 μF 110
VEN(HI) Enable high (enabled) 2.7 V ≤ VIN ≤ 5.5 V 1.7 VIN V
VEN(LO) Enable low (shutdown) 2.7 V ≤ VIN ≤ 5.5 V 0 0.7 V
IEN(HI) Enable pin current, enabled VEN = 0 V –1 1 μA
UVLO Undervoltage lockout VCC rising 2.25 2.65 V
Hysteresis 100 mV
Tsd Thermal shutdown temperature Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 140
TJ Operating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. TPS79650 is tested at VIN = 5.5 V.
(2) Tolerance of external resistors not included in this specification.
(3) VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7 V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.

6.6 Typical Characteristics

At VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C, unless otherwise noted.
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_vo_v_io4v_lvs351.gif
Figure 1. TPS79630 Output Voltage vs Output Current
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_gc_tj_38v_lvs351.gif
Figure 3. TPS79628 Ground Current vs
Junction Temperature
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc1_osnd_f_lvs351.gif
Figure 5. TPS79630 Output Spectral Noise Density vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_rms_bp_lvs351.gif
Figure 7. TPS79630 Root Mean Squared Output Noise vs Bypass Capacitance
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_rr_f01_lvs351.gif
Figure 9. TPS79630 Ripple Rejection vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_rr_f22_lvs351.gif
Figure 11. TPS79630 Ripple Rejection vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_ltr18_lvs351.gif
Figure 13. TPS79618 Line Transient Response
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_ltr28_lvs351.gif
Figure 15. TPS79628 Load Transient Response
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_dv_io30_lvs351.gif
Figure 17. TPS79630 Dropout Voltage vs Output Current
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_esr_io1_lvs351.gif
Figure 19. TPS79630 Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_trsesr_io_lvs351.gif
Figure 21. TPS79630 Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_vo_tj_38v_lvs351.gif
Figure 2. TPS79628 Output Voltage vs
Junction Temperature
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_osnd_f22c_lvs351.gif
Figure 4. TPS79630 Output Spectral Noise Density vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc2_osnd_f_lvs351.gif
Figure 6. TPS79630 Output Spectral Noise Density vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_vdo_tj_lvs351.gif
Figure 8. TPS79628 Dropout Voltage vs
Junction Temperature
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_rr_f1_lvs351.gif
Figure 10. TPS79630 Ripple Rejection vs Frequency
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_v_t_lvs351.gif
Figure 12. Start-Up Time
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_ltr30_lvs351.gif
Figure 14. TPS79630 Line Transient Response
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_pupd25_lvs351.gif
Figure 16. TPS79625 Power Up/Power Down
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_dv_io01_lvs351.gif
Figure 18. TPS79601 Dropout Voltage vs Input Voltage
TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650 tc_esr_io36_lvs351.gif
Figure 20. TPS79630 Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
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