5 Pin Configuration and Functions

Figure 5-1 DDC Package (Fixed),5-Pin SOT-23-THIN(Top View)

Figure 5-3 YZU Package (Fixed),5-Pin DSBGA(Top View)

Figure 5-5 DRV Package (Fixed),6-Pin WSON With Exposed Thermal Pad(Top View)

Figure 5-2 DDC Package (Adjustable),5-Pin SOT-23-THIN(Top View)

Figure 5-4 YZU Package (Adjustable),5-Pin DSBGA (Top View)

Figure 5-6 DRV Package (Adjustable),6-Pin WSON With Exposed Thermal Pad (Top View)

Table 5-1 Pin Functions

PIN				I/O	DESCRIPTION
NAME	DDC	YZU	DRV	I/O	DESCRIPTION
IN	1	C3	6	I	Input supply.
GND	2	B2	3, Pad	—	Ground. The pad must be tied to GND.
EN	3	A1	4	I	Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
NR	4	A3	2	—	Fixed voltage versions only. Noise reduction; connecting this pin to an external capacitor bypasses noise generated by the internal band gap. This capacitor allows output noise to be reduced to very low levels.
FB	4	A3	2	I	Adjustable voltage version only. Feedback; this pin is the input to the control loop error amplifier, and sets the output voltage of the device.
OUT	5	C1	1	O	Output of the regulator. To assure stability, a small ceramic capacitor (total typical capacitance ≥ 2 μF) is required from this pin to ground.
N/C	—	—	5	—	Not internally connected. This pin must either be left open, or tied to GND.