TPS7A16 具有使能和电源正常指示功能的60V、5µA IQ、100mA、低压降稳压器
- ZHCS237F December 2011 – October 2015 TPS7A16
  
  PRODUCTION DATA.

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TPS7A16 具有使能和电源正常指示功能的60V、5µA IQ、100mA、低压降稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

宽输入电压范围：3V 至 60V
超低静态电流：5µA
关断时的静态电流：1µA
输出电流：100mA
低压降电压：电流为 20mA 时为 60mV
精度：2%
可提供：
- 固定输出电压：3.3V，5V
- 可调节输出电压：1.2V 至 18.5V
具有可编程延迟的电源正常指示功能
限流和热关断保护
与陶瓷输出电容搭配使用时可保持稳定：
≥ 2.2µF
封装：高耐热性能微型小外形尺寸 (MSOP)-8 和小外形尺寸无引线 (SON)-8 封装 PowerPAD™
工作温度范围：
–40°C 至 125°C

2 应用

笔记本个人电脑 (PC)、数字电视和私有局域网 (LAN) 系统电源
用于电动工具和其它由电池供电的微处理器和微控制器系统的高节数电池组
车载音频、导航、信息娱乐、和其它汽车系统
烟雾和 CO₂ 探测器以及电池供电类警报和安全系统

3 说明

TPS7A16 系列超低功耗、低降压 (LDO) 稳压器提供超低静态电流、高输入电压和小型化、高散热性能封装所具备的优势。

TPS7A16 系列器件针对连续或断续（备用电源）电池供电应用而设计，超低静态电流在此类应用中对于延长系统电池寿命至关重要。

TPS7A16 系列米6体育平台手机版_好二三四提供一个与标准互补金属氧化物半导体 (CMOS) 逻辑电路兼容的使能引脚 (EN) 和一个具有用户可编程延迟的集成开漏高电平有效的电源正常输出 (PG)。这些引脚专用于需要进行电源轨排序、基于微控制器的电池供电类应用。

此外，TPS7A16 器件非常适用于从多节电池解决方案生成低压电源（从多节电动工具组到汽车应用）；该器件不但能够提供一个稳压良好的电压轨，而且还能够承受瞬态电压并在电压瞬态期间保持稳压状态。这些功能意味着电涌保护电路更加简单且更为经济高效。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS7A16	HVSSOP (8)	3.00mm × 3.00mm
TPS7A16	VSON (8)	3.00mm × 3.00mm

要了解所有可用封装，请参见数据表末尾的封装选项附录。

典型应用电路原理图

静态电流与输入电压间的关系

4 修订历史记录

Changes from E Revision (August 2015) to F Revision

Changed ψ_JB value in Thermal Information table from 141.2 to 11.2 (typo) Go

Changes from D Revision (January 2014) to E Revision

Added ESD 额定值表，特性描述 部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go
Changed MIN value of Regulated output from 1.2 to 1.169 Go
Changed MAX value of Regulated output from 18 to 18.5 Go
Changed MAX value of Operating junction temperature from 150 to 125 Go
Changed value in Power-Good section from 5.5-V to 5-VGo

Changes from C Revision (November 2013) to D Revision

Changed Feedback Current min, typ, and max values from –1.0, 0.0, and 1.0 to –0.1, –0.01, and 0.1, respectivelyGo
Changed Enable Current typ value from 0.01 to –0.01Go

Changes from B Revision (April 2013) to C Revision

已将 DRB 封装从米6体育平台手机版_好二三四预览改为生产数据Go
Added DRB package to thermal informationGo
Changed Figure 4 Y-axis unit from V to mV (typo)Go

Changes from A Revision (December 2011) to B Revision

已添加 DRB 封装的米6体育平台手机版_好二三四预览至数据表。Go

Changes from * Revision (December 2011) to A Revision

已将数据表由“米6体育平台手机版_好二三四预览”改为“量产数据”Go

5 Pin Configuration and Functions

DGN Package

8-Pin HVSSOP

Top View

DRB Package

8-Pin VSON

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
DELAY	7	O	Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not needed.
EN	5	I	Enable pin. This pin turns the regulator on or off. If V_EN ≥ V_{EN_HI}, the regulator is enabled. If V_EN ≤ V_{EN_LO}, the regulator is disabled. If not used, the EN pin can be connected to IN. Make sure that V_EN ≤ V_IN at all times.
FB/DNC	2	I	For the adjustable version (TPS7A1601), the feedback pin is the input to the control-loop error amplifier. This pin is used to set the output voltage of the device when the regulator output voltage is set by external resistors. For the fixed voltage versions: Do not connect to this pin. Do not route this pin to any electrical net, not even GND or IN.
GND	4	GND	Ground pin.
IN	8	IN	Regulator input supply pin. A capacitor ≥ 0.1 µF must be tied from this pin to ground to assure stability. TI recommends connecting a 10-µF ceramic capacitor from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source impedances are encountered.
NC	6	—	This pin can be left open or tied to any voltage between GND and IN.
OUT	1	O	Regulator output pin. A capacitor ≥ 2.2 µF must be tied from this pin to ground to assure stability. TI recommends connecting a 10-µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize AC performance.
PG	3	O	Power-good pin. Open collector output; leave open or connect to GND if the power-good function is not needed.
PowerPAD	—	—	Solder to printed-circuit-board (PCB) to enhance thermal performance. Although it can be left floating, TI highly recommends connecting the PowerPAD to the GND plane.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range –40°C ≤ T_J ≤ 125°C (unless otherwise noted).⁽¹⁾

		MIN	MAX	UNIT
Voltage	IN pin to GND pin	–0.3	62	V
	OUT pin to GND pin	–0.3	20
	OUT pin to IN pin	–62	0.3
	FB pin to GND pin	–0.3	3
	FB pin to IN pin	–62	0.3
	EN pin to IN pin	–62	0.3
	EN pin to GND pin	–0.3	62
	PG pin to GND pin	–0.3	5.5
	DELAY pin to GND pin	–0.3	5.5
Current	Peak output	Internally limited
Temperature	Operating virtual junction, T_J	–40	150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Unregulated input	3	60	V
V_OUT	Regulated output	1.169	18.5	V
EN		0	40	V
DELAY		0	5	V
PG		0	5	V
T_J	Operating junction temperature range	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A1601		UNIT
		DGN (HVSSOP)	DRB (VSON)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	66.2	44.5	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	45.9	49.5	°C/W
R_θJB	Junction-to-board thermal resistance	34.6	11.3	°C/W
ψ_JT	Junction-to-top characterization parameter	1.9	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	34.3	11.2	°C/W
R_θJC(bot)	Junction-to-case(bottom) thermal resistance	14.9	4.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At T_J= –40°C to 125°C, V_IN = V_OUT(NOM) + 0.5 V or V_IN = 3 V (whichever is greater), V_EN = V_IN, I_OUT = 10 µA, C_IN = 1 μF, C_OUT = 2.2 μF, and FB tied to OUT, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input voltage range		3		60	V
V_REF	Internal reference	T_J = 25°C, V_FB = V_REF, V_IN = 3 V, I_OUT = 10 μA	1.169	1.193	1.217	V
V_UVLO	Undervoltage lockout threshold			2.7		V
V_OUT	Output voltage range	V_IN ≥ V_OUT(NOM) + 0.5 V	V_REF		18.5	V
	Nominal accuracy	T_J = 25°C, V_IN = 3 V, I_OUT = 10 μA	–2%		2%	V_OUT
	Overall accuracy	V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 60 V⁽¹⁾ 10 µA ≤ I_OUT ≤ 100 mA	–2%		2%	V_OUT
ΔV_O(ΔVI)	Line regulation	3 V ≤ V_IN ≤ 60 V		±1%		V_OUT
ΔV_O(ΔIO)	Load regulation	10 µA ≤ I_OUT ≤ 100 mA		±1%		V_OUT
V_DO	Dropout voltage	V_IN = 4.5 V, V_OUT(NOM) = 5 V, I_OUT = 20 mA		60		mV
V_DO	Dropout voltage	V_IN = 4.5 V, V_OUT(NOM) = 5 V, I_OUT = 100 mA		265	500	mV
I_LIM	Current limit	V_OUT = 90% V_OUT(NOM), V_IN = 3 V	101	225	400	mA
I_GND	Ground current	3 V ≤ V_IN ≤ 60 V, I_OUT = 10 µA		5	15	μA
I_GND	Ground current	I_OUT = 100 mA		5		μA
I_SHDN	Shutdown supply current	V_EN = 0.4 V		0.59	5	μA
I_FB	Feedback current⁽²⁾		–0.1	–0.01	0.1	µA
I_EN	Enable current	3 V ≤ V_IN ≤ 12 V, V_IN = V_EN	–1	–0.01	1	μA
V_{EN_HI}	Enable high-level voltage		1.2			V
V_{EN_LO}	Enable low- level voltage				0.3	V
V_IT	PG trip threshold	OUT pin floating, V_FB increasing, V_IN ≥ V_{IN_MIN}	85%		95%	V_OUT
V_IT	PG trip threshold	OUT pin floating, V_FB decreasing, V_IN ≥ V_{IN_MIN}	83%		93%	V_OUT
V_HYS	PG trip hysteresis			2.3%	4%	V_OUT
V_{PG, LO}	PG output low voltage	OUT pin floating, V_FB = 80% V_REF, I_PG= 1mA			0.4	V
I_{PG, LKG}	PG leakage current	V_PG= V_OUT(NOM)	–1		1	μA
I_DELAY	DELAY pin current			1	2	μA
PSRR	Power-supply rejection ratio	V_IN = 3 V, V_OUT(NOM) = V_REF, C_OUT = 10 μF, f = 100 Hz		50		dB
T_SD	Thermal shutdown temperature	Shutdown, temperature increasing		170		°C
T_SD	Thermal shutdown temperature	Reset, temperature decreasing		150		°C
T_J	Operating junction temperature range		–40		125	°C

(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (V_IN – V_OUT) × I_OUT =
(24 V – V_REF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking.

(2) I_FB > 0 flows out of the device.

6.6 Typical Characteristics

At T_J= –40°C to 125°C, V_IN = V_OUT(NOM) + 0.5 V or V_IN = 3 V (whichever is greater), V_EN = V_IN, I_OUT = 10 µA, C_IN = 1 μF, C_OUT = 2.2 μF, and FB tied to OUT, unless otherwise noted.

Figure 1. Quiescent Current vs Input Voltage