ZHCSQT5 July   2022 TPS7A57

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

说明

TPS7A57 是一款低噪声 (2.45µVRMS)、低压降线性稳压器 (LDO),可提供 5A 电流,压降仅为 75mV(独立于输出电压)。该器件的输出电压可通过一个外部电阻进行调节,范围为 0.5V 至 5.2V。TPS7A57 集低噪声、高 PSRR(1MHz 时为 36dB)和高输出电流能力等特性一体,专为雷达电源、通信和成像应用中的噪声敏感型组件(例如射频放大器、雷达传感器、SERDES 和模拟芯片组)供电而设计。

需要以低输入和低输出 (LILO) 电压运行的数字负载(例如应用特定集成电路 (ASIC)、现场可编程门阵列 (FPGA) 和数字信号处理器 (DSP))还能够从出色精度(在负载、线路和温度范围内可达 1%)、遥感功能、出色的瞬态性能和软启动功能中受益,以提供出色的系统性能。凭借多功能性、高性能和小尺寸解决方案,该 LDO 成为模数转换器 (ADC)、数模转换器 (DAC) 和成像传感器等高电流模拟负载以及串行器/解串器 (SerDes)、FPGA 和 DSP 等数字负载的理想选择。

封装信息(1)
器件型号封装封装尺寸(标称值)
TPS7A57WQFN (16)3.00mm × 3.00mm
如需了解所有可用封装,请参阅数据表末尾的可订购米6体育平台手机版_好二三四附录。
GUID-20211102-SS0I-6Q48-PCBF-2GXSVHLCDCPF-low.gif典型应用电路
GUID-20220504-SS0I-LM6C-GFN2-MN6RN5KXM6DT-low.png5A、1.2VIN、0.9VOUT PSRR,已启用 CP