ZHCSQT5 July 2022 TPS7A57
PRODUCTION DATA
As described in the Section 7.2, the PG pin is a open-drain MOSFET driven by a Schmitt trigger. The Schmitt trigger compares the SNS pin voltage to a preselected voltage equal to 90% that of the reference voltage.
As mentioned in the Section 6.3 table, the pullup resistance must be between 10 kΩ and 100 kΩ for optimal performance. If the PG functionality is not desired, the PG pin can either be left floating or connected to GND.
There are two UVLO circuits present on the BIAS rail, one referenced to GND (VUVLO(BIAS)) and one referenced to VREF (VUVLO(BIAS) – VREF). A false PG event can occur as a result of logic priorities when the charge pump is disabled.
To eliminate any false PG events, consider setting VBIAS 3.2 V above VOUT.
Table 8-5 describes the various UVLO behaviors.
| VIN | VUVLO(BIAS) RISING | VUVLO(BIAS) FALLING | VUVLO(BIAS) – VREF RISING | VUVLO(BIAS) – VREF FALLING |
|---|---|---|---|---|
| 0.5 V | 2.8 V | 2.685 V | 2.1 + 0.5 = 2.6 V | 1.86 + 0.5 = 2.36 V |
| 0.7 V | 2.8 V | 2.685 V | 2.1 + 0.7 = 2.8 V | 1.86 + 0.7 = 2.56 V |
| 1.4 V | 2.8 V | 2.685 V | 2.1 + 1.4 = 3.5 V | 1.86 + 1.4 = 3.26 V |
| 5.2 V | 2.8 V | 2.685 V | 2.1 + 5.2 = 7.3 V | 1.86 + 5.2 = 7.06 V |