ZHCSQT5 July   2022 TPS7A57

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating temperature range (TJ = –40 °C to +125 °C), VIN(NOM) = VOUT(NOM) + 0.4 V, VCP_EN = 1.8 V, VBIAS = 0 V, IOUT = 0 A, VEN = 1.8 V, CIN  = 10 µF, COUT = 22 μF, CBIAS = 0 nF, CNR/SS = 100 nF, SNS pin shorted to OUT pin, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO(IN) Input supply UVLO with BIAS VIN rising, VCP_EN = 1.8 V (3 V ≤ VBIAS ≤ 11 V) and VCP_EN = 0 V  (VOUT + 3.2 V ≤ VBIAS ≤ 11 V) 0.67 0.7 V
VHYS(UVLO_IN) Input supply UVLO hysteresis with BIAS VCP_EN = 1.8 V (3 V ≤ VBIAS ≤ 11 V) and VCP_EN = 0 V (VOUT + 3.2 V ≤ VBIAS ≤ 11 V) 50 mV
VUVLO(IN) Input supply UVLO without BIAS VIN rising, VCP_EN = 1.8 V  1.07 1.1 V
VHYS(UVLO_IN) Input supply UVLO hysteresis without BIAS VCP_EN = 1.8 V 50 mV
VUVLO(BIAS) – VREF BIAS UVLO relative to VREF without CP VBIAS rising, VCP_EN = 0 V, 1.4 V ≤ VREF ≤ 5.2 V 2.1 2.95 V
VHYS(UVLO_BIAS - REF) BIAS UVLO relative to VREF hysteresis without CP VCP_EN = 0 V, 1.4 V ≤ VREF ≤ 5.2 V 240 mV
VUVLO(BIAS) BIAS UVLO with CP VBIAS rising, VCP_EN = 1.8 V, 0.7 V ≤ VIN < 1.1 V 2.8 2.95 V
VHYS(UVLO_BIAS) BIAS UVLO hysteresis with CP VCP_EN = 1.8 V, 0.7 V ≤ VIN < 1.1 V 115 mV
INR/SS NR/SS fast start-up charging current VNR/SS = GND, VIN = 1.1 V 0.2 mA
VOUT Output voltage accuracy (1) 0.5 V ≤ VOUT ≤ 5.2 V,
0 A ≤ IOUT ≤ 5 A,
VCP_EN = 0 V, VOUT + 3.2 V ≤ VBIAS ≤ 11 V; 0.7 V ≤ VIN ≤ 6 V (6),
VCP_EN = 1.8 V, 3 V ≤ VBIAS ≤ 11 V, 0.7 V ≤ VIN ≤ 6 V (6),
VCP_EN = 1.8 V, no BIAS, 1.1 V ≤ VIN ≤ 6 V		 –1 1 %
IREF REF current pin VIN = 1.1 V, VCP_EN = 1.8 V, VOUT = 0.5 V,
ILOAD = 0 A, VBIAS = 0 V		 50 µA
VCP_EN = 0 V (CP disabled),
0.7 V ≤ VIN ≤ 6 V (5)(6), 0.5 V ≤ VOUT ≤ 5.2 V, 
VOUT + 3.2 V ≤ VBIAS ≤ 11 V,
0 A ≤ IOUT ≤ 5 A		 –1 1 %
VCP_EN = 1.8 V (CP enabled, VBIAS = 0 V),
1.1 V ≤ VIN ≤ 6 V (5), 0.5 V ≤ VOUT ≤ 5.2 V,
0 A ≤ IOUT ≤ 5 A (6)		 –1 1
VCP_EN = 1.8 V (CP enabled),
0.7 V ≤ VIN ≤ 6 V (5), 0.5 V ≤ VOUT ≤ 5.2 V,
3 V ≤ VBIAS ≤ 11 V, 0 A ≤ IOUT ≤ 5 A		 –1 1
VOS Output offset voltage (VNR/SS - VOUT) VIN = 0.7 V, VOUT = 0.5 V, IOUT = 0 A,
VCP_EN = 1.8 V, 3 V ≤ VBIAS ≤ 11 V,
VCP_EN = 0 V, VOUT + 3.2 V ≤ VBIAS ≤ 11 V		 –1 1 mV
0.7 V ≤ VIN ≤ 6 V (5)(6), 0.5 V ≤ VOUT ≤ 5.2 V,
VCP_EN = 1.8 V, 3 V ≤ VBIAS ≤ 11 V,
0 A ≤ IOUT ≤ 5 A		 –2 2
1.1 V ≤ VIN ≤ 6.0 V (5)(6), 0.5 V ≤ VOUT ≤ 5.2 V,
VCP_EN = 1.8 V, VBIAS = 0 V,
0 A ≤ IOUT ≤ 5 A		 –2 2
0.7 V ≤ VIN ≤ 6 V (5)(6), 0.5 V ≤ VOUT ≤ 5.2 V,
VCP_EN = 0 V, VOUT + 3.2 V ≤ VBIAS ≤ 11 V,
0 A ≤ IOUT ≤ 5 A		 –2 2
ΔIREF(ΔVBIAS) Line regulation: ΔIREF VOUT + 3.2 V ≤ VBIAS ≤ 11 V, VIN = 0.7V, VOUT = 0.5 V,
VCP_EN = 0 V, IOUT = 0 A		 0.15 nA/V
ΔVOS(ΔVBIAS) Line regulation: ΔVOS VOUT + 3.2 V ≤ VBIAS ≤ 11 V, VIN = 0.7 V, VOUT = 0.5 V,
VCP_EN = 0 V, IOUT = 0 A		 0.06 µV/V
ΔIREF(ΔVIN) Line regulation: ΔIREF 1.1 V ≤ VIN ≤ 6 V, VOUT = 0.5 V, VCP_EN = 1.8 V,
IOUT = 0 A, VBIAS = 0 V		 0.03 nA/V
ΔVOS(ΔVIN) Line regulation: ΔVOS 1.1 V ≤ VIN ≤ 6 V, VOUT = 0.5 V, VCP_EN = 1.8 V,
IOUT = 0 A, VBIAS = 0 V		 0.01 µV/V
ΔVOS(ΔIOUT) Load regulation: ΔVOS VIN = 0.7 V, VOUT = 0.5 V, VCP_EN = 0 V, 0 A ≤ IOUT ≤ 5 A,
VOUT + 3.2 V ≤ VBIAS ≤ 11 V		 5 µV/A
VOUT = 5.2 V, VCP_EN = 1.8 V, 0 A ≤ IOUT ≤ 5 A,
VBIAS = 0 V		 175
Change in IREF vs VREF 0.5 V ≤ VREF ≤ 5.2 V, VIN = 6 V, IOUT = 0 A, 
VCP_EN = 1.8 V, VBIAS = 0 V		 4.4 nA
Change in VOS vs VREF 0.25 mV
VDO Dropout voltage (3) 1.1 V ≤ VIN ≤ 5.3 V, IOUT = 5 A, VCP_EN = 1.8 V,
–40°C ≤ TJ ≤ +125°C		 75 110 mV
1.1 V ≤ VIN ≤ 5.3 V, IOUT = 5 A, VCP_EN = 1.8 V,
–40°C ≤ TJ ≤ +85°C		 100
0.7 V ≤ VIN ≤ 1.1 V, IOUT = 5 A, VCP_EN = 1.8 V,
VBIAS = 3 V, –40°C ≤ TJ ≤ +125°C		 75 110
0.7 V ≤ VIN ≤ 1.1 V, IOUT = 5 A, VCP_EN = 1.8 V,
VBIAS = 3 V, –40 °C ≤ TJ ≤ +85 °C		 100
0.7 V ≤ VIN ≤ 5.3 V, IOUT = 5 A, VCP_EN = 0 V,
VBIAS = VIN + 3.2 V, –40°C ≤ TJ ≤ +125°C		 75 110
0.7 V ≤ VIN ≤ 5.3 V, IOUT = 5 A, VCP_EN = 0 V,
VBIAS = VIN + 3.2 V, –40°C ≤ TJ ≤ +85°C		 100
ILIM Output current limit VOUT forced at 0.9 × VOUT(NOM),
VOUT(NOM) = 5.2 V,
VIN = VOUT(NOM) + 400 mV,
VCP_EN = 0 V, VBIAS = VOUT + 3.2 V		 5.2 6.0 6.7 A
ISC Short circuit current limit RLOAD = 10 mΩ, under foldback operation 4 A
IBIAS BIAS pin current VIN = 6 V, IOUT = 0 A, VCP_EN = 0 V, VBIAS = VOUT + 3.2 V,
VOUT = 5.2 V		 1 1.5 2 mA
VIN = 0.7 V, IOUT = 5 A, VOUT = 0.5 V,
VCP_EN = 1.8 V, 3.0 V ≤ VBIAS ≤ 11 V		 8 11 15
IGND GND pin current VIN = 6 V, IOUT = 0 A, VCP_EN = 0 V, VBIAS = VOUT + 3.2 V,
VOUT = 5.2 V		 3.5 5 6.5 mA
VIN = 5.6 V, IOUT = 5 A, VOUT = 5.2 V, VCP_EN = 1.8 V,
VBIAS = 0 V		 16.5
VIN = 1.1 V, IOUT = 5 A, VOUT = 0.5 V,
VCP_EN = 1.8 V, VBIAS = 0 V		 12 17.5 24
VIN = 0.7 V, IOUT = 5 A, VOUT = 0.5 V,
VCP_EN = 1.8 V, 3 V ≤ VBIAS ≤ 11 V		 11 16.5 23
VIN = 0.7 V, IOUT = 5 A, VOUT = 0.5 V,
VCP_EN = 0 V, VOUT + 3.2 V ≤ VBIAS ≤ 11 V		 5 7 9
ISDN Shutdown GND pin current PG = (open), VIN = 6 V, VEN = 0.4 V, VCP_EN = 1.8 V,
VBIAS = 0 V		 100 300 µA
PG = (open), VIN = 6 V, VEN = 0.4 V, VCP_EN = 0.4 V,
VBIAS = 11 V		 150 450
IEN EN pin current VIN = 6 V, 0 V ≤ VEN ≤ 6 V, VCP_EN = 1.8 V, VBIAS = 0 V -5 5 µA
VIH(EN) EN trip point rising (turn-on) VIN = 1.1 V (VCP_EN = 1.8 V) or
VBIAS ≥ 3 V (VCP_EN = 0 V)		 0.62 0.65 0.68 V
VHYS(EN) EN trip point hysteresis VIN = 1.1 V (VCP_EN = 1.8 V) or
VBIAS ≥ 3 V (VCP_EN = 0 V)		 40 mV
ICP_EN CP_EN pin current VIN = 6.0 V, 0 V ≤ VCP_EN ≤ 6 V –5 5 µA
VIH(CP_EN) CP_EN trip point rising (turn-on) 1.1 V ≤ VIN ≤ 6 V, VEN = 1.8 V, VBIAS = 0 V,
0.7 V ≤ VIN ≤ 1.1 V, VEN = 1.8 V, VBIAS = 3 V		 0.57 0.6 0.63 V
VHYS(CP_EN) CP_EN trip point hysteresis 1.1 V ≤ VIN ≤ 6 V, VEN = 1.8 V, VBIAS = 0 V,
0.7 V ≤ VIN ≤ 1.1 V, VEN = 1.8 V, VBIAS = 3 V		 56 mV
VIT(PG) PG pin threshold For PG transitioning low with falling VOUT, VIN = 1.1 V,
VBIAS = 0 V, VCP_EN = 1.8 V, VOUT < VIT(PG), IPG = –1 mA (current into device)		 87 90 93 %
VHYS(PG) PG pin hysteresis VIN = 1.1 V, VBIAS = 0 V, VCP_EN = 1.8 V, VOUT < VIT(PG),
IPG = –1 mA (current into device)		 2 %
VOL(PG) PG pin low-level output voltage VIN = 1.1 V, VBIAS = 0 V, VCP_EN = 1.8 V, VOUT < VIT(PG),
IPG = –1 mA (current into device)		 0.4 V
ILKG(PG) PG pin leakage current VPG = 6 V, VOUT > VIT(PG), VIN = 1.1 V, VBIAS = 0 V,
VCP_EN = 1.8 V		 1 µA
PSRR Power-supply ripple rejection f = 1 MHz, VIN = 0.8 V, VOUT(NOM) = 0.5 V, VCP_EN = 0 V,
VBIAS = VOUT + 3.2 V, IOUT = 5 A, CNR/SS = 4.7 µF		 40 dB
f = 1 MHz, VIN = 0.9 V, VOUT(NOM) = 0.5 V,  VCP_EN = 0 V,
VBIAS = VOUT + 3.2 V, IOUT = 5 A, CNR/SS = 4.7 µF		 40
f = 1 MHz, VIN = 5.3 V, VOUT(NOM) = 5 V, VCP_EN = 1.8 V,
VBIAS = 0 V, IOUT = 5 A, CNR/SS = 4.7 µF		 40
f = 1 MHz, VIN = 5.4 V, VOUT(NOM) = 5 V, , VCP_EN = 1.8 V,
VBIAS = 0 V, IOUT = 5 A, CNR/SS = 4.7 µF		 36
Vn Output noise voltage BW = 10 Hz to 100 kHz,
0.7V  ≤ VIN ≤ 6 V, 0.5 V ≤ VOUT ≤ 5.2 V, IOUT = 5 A,
CNR/SS = 4.7 µF, VCP_EN = 0 V, VBIAS = VOUT + 3.2 V		 2.49 µVRMS
BW = 10 Hz to 100 kHz,
1.1 V ≤ VIN ≤ 6 V, 0.5 V ≤ VOUT ≤ 5.2 V,
IOUT = 5 A, CNR/SS = 4.7 µF, VCP_EN = 1.8 V, VBIAS = 0 V		 2.49
Noise spectral density f = 100 Hz, 0.7 V ≤ VIN ≤ 6 V,
0.5 V ≤ VOUT ≤ 5.2 V, IOUT = 5 A, CNR/SS = 4.7 µF,
VCP_EN = 0 V, VBIAS = VOUT + 3.2 V		 20 nV/√Hz
f = 1 kHz, 0.7 V ≤ VIN ≤ 6 V, 0.5 V ≤ VOUT ≤ 5.2 V,
IOUT = 5 A, CNR/SS = 4.7 µF, VCP_EN = 0 V, 
VBIAS = VOUT + 3.2 V		 9
f = 10 kHz, 0.7 V ≤ VIN ≤ 6 V, 0.5 V ≤ VOUT ≤ 5.2 V,
IOUT = 5 A, CNR/SS = 4.7 µF, VCP_EN = 0 V, 
VBIAS = VOUT + 3.2 V		 6
RDIS Output pin active discharge resistance VIN = 1.1 V, VCP_EN = 1.8 V, VBIAS = 0 V, VEN = 0 V 110 Ω
RNR/SS_DIS NR/SS pin active discharge resistance VIN = 1.1 V, VCP_EN = 1.8 V, VBIAS = 0 V, VEN = 0 V 100 Ω
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing 165 °C
TSD(reset) Thermal shutdown reset temperature Reset, temperature decreasing 150 °C
(1) Max power dissipation of 2 W.
(2) Limited by pulse max power dissipation. For 0 mA ≤ IOUT ≤ 2.5 A, VIN = 6 V, 0 mA ≤ IOUT ≤ 5 A, VIN = 5.6 V.
(3) VREF = VIN, VSNS = 97% × VREF.
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