| THERMAL METRIC(1)(2) | TPS7A7100(3) | UNIT |
|---|
| RGW (VQFN) | RGT (VQFN) |
|---|
| 20 PINS | 16 PINS |
|---|
| RθJA | Junction-to-ambient thermal resistance(4) | 35.7 | 44.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance(5) | 33.6 | 54.3 | °C/W |
| RθJB | Junction-to-board thermal resistance(6) | 15.2 | 17.2 | °C/W |
| ψJT | Junction-to-top characterization parameter(7) | 0.4 | 1.1 | °C/W |
| ψJB | Junction-to-board characterization parameter(8) | 15.4 | 17.2 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance(9) | 3.8 | 3.8 | °C/W |
(2) For thermal estimates of this device based on printed-circuit-board (PCB)
copper area, see the
TI PCB thermal calculator.
(3) Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
- i. RGW: The exposed pad is connected to the PCB ground layer through a 4 × 4 thermal via array.
ii. RGT: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array. - i. RGW: Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage.
ii .RGT: Both the top and bottom copper layers have a dedicated pattern for 5% copper coverage. - These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the
junction temperature of a device in a real system and is extracted from the
simulation data to obtain RθJA using a procedure described in
JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the
junction temperature of a device in a real system and is extracted from the
simulation data to obtain RθJA using a procedure described in
JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.