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ZHCSBR4A April 2014 – June 2014 TPS7A8101-Q1

PRODUCTION DATA.

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9 Application and Implementation

9.1 Application Information

The TPS7A8101-Q1 device belongs to a family of new-generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with very low headroom (V_I – V_O). A noise-reduction capacitor (C_(NR)) at the NR pin and a bypass capacitor (C_(BYPASS)) decrease noise generated by the bandgap reference in order to improve PSRR, while a quick-start circuit fast-charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current-limit, and thermal protection, and is fully specified from –40°C to 125°C.

9.2 Typical Application

Figure 31 shows the connections for the device.

Figure 31. Typical Application Circuit

The voltage on the FB pin sets the output voltage and is determined by the values of the resistors R1 and R2. Use Equation 2 to calculate the values of R1 and R2 any voltage.

Equation 2.

Table 1 lists sample resistor values for common output voltages. In Table 1, E96 series resistors are used, and all values meet 1% of the target V_O, assuming resistors with zero error. For the actual design, pay attention to any resistor error-factors. Using lower values for R1 and R2 reduces the noise injected into the FB pin.

9.2.1 Design Requirements

9.2.1.1 Dropout Voltage

The TPS7A8101-Q1 device uses a PMOS pass transistor to achieve low dropout. When (V_I – V_Onom) is less than the dropout voltage (V_DO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the r_DS(on) of the PMOS pass element. V_DO is proportional to the output current because the PMOS device in dropout functions in the same way as a resistor.

As with any linear regulator, PSRR and transient responses are degraded as (V_I – V_O) approaches dropout. Figure 19 and Figure 20 in the Typical Characteristics section shown this effect.

9.2.1.2 Minimum Load

The TPS7A8101-Q1 device is stable and functions well with no output load. Traditional PMOS-LDO regulators suffer from lower loop gain at very light output loads. The TPS7A8101-Q1 device employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.

9.2.1.3 Input And Output Capacitor Requirements

Although an input capacitor is not required for stability, connecting a 0.1-µF to 1-µF low-equivalent series-resistance (ESR) capacitor from the input supply near the regulator to ground is good analog-design practice. This capacitor counteracts reactive input sources and improves transient response and ripple rejection. A higher-value capacitor may be necessary if large, fast load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.

The TPS7A8101-Q1 device is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or larger. This device was evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and 0805 size (2 mm × 1,25 mm).

X5R-type and X7R-type capacitors are highly recommended because they have minimal variation in capacitance and ESR over temperature. The maximum ESR should be less than 1 Ω.

Table 1. Recommended Feedback Resistor Values for Common Output Voltages

V_O	R1	R2
0.8 V	0 Ω (Short)	10 kΩ
1 V	2.49 kΩ	10 kΩ
1.2 V	4.99 kΩ	10 kΩ
1.5 V	8.87 kΩ	10 kΩ
1.8 V	12.5 kΩ	10 kΩ
2.5 V	21 kΩ	10 kΩ
3.3 V	30.9 kΩ	10 kΩ
5 V	52.3 kΩ	10 kΩ

Table 2. Recommended Capacitor Values

NAME	DESCRIPTION	VALUE
C_(NR)	Noise-reduction capacitor between the NR and GND pins	470 nF
C_(BYPASS)	Noise-reduction capacitor across R1	470 nF
C_(OUTPUT)	Output capacitor	10 µF
C_(IN)	Input capacitor	10 µF

9.2.1.4 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the duration of the transient response. Using a larger noise-reduction capacitor (C_(NR)), bypass capacitor (C_(BYPASS)), or both types of capacitors can improve line-transient performance.

9.2.2 Detailed Design Procedure

9.2.2.1 Output Noise

In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (C_(NR)) is used with the TPS7A8101-Q1 device, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor-divider and the error-amplifier input. If a bypass capacitor (C_(BYPASS)) across the high-side feedback resistor (R1) is used with the TPS7A8101-Q1 device, noise from these other sources can also be significantly reduced.

To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF bypass capacitor.

9.2.3 Application Curves

C_(NR) = C_(BYPASS) = 470 nF	C_(OUT) = 10 µF	C_(IN) = 0 F

Figure 32. PSRR vs Frequency

V_I– V_O = 0.5 V	C_(IN) = 0 F	C_(OUT) = 10 µF
C_(NR) = C_(BYPASS) = 470 nF

Figure 34. PSRR vs Frequency

23.54 µV_RMS(I_O = 100 mA)	C_(IN) = 10 µF	V_I– V_O = 0.5 V
23.71 µV_RMS (I_O = 750 mA)	C_(NR) = 470 nF	C_(OUT) = 10 µF
22.78 µV_RMS (I_O = 1 A)	C_(BYPASS) = 470 nF

Figure 36. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

23.54 µV_RMS(C_O = 10 µF)	C_(IN) = 10 µF	V_I– V_O = 0.5 V
23.91 µV_RMS (C_O = 22 µF)	C_(NR) = 470 nF	C_(OUT) = 10 µF
22.78 µV_RMS (C_O = 100 µF)	C_(BYPASS) = 470 nF

Figure 38. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

V_I = 3.8 V → 4.8 V → 3.8 V
	I_O = 500 mA

Figure 40. Line Transient Response

R_L = 33 Ω	C_(NR) = 470 nF	C_(BYPASS) = 470 nF
C_(OUT) = 10 µF	C_(IN) = 10 µF

Figure 42. Enable Pulse Response, See (1) in Figure 43

V_I– V_O = 1 V	C_(IN) = 0 F	C_(OUT) = 10 µF
C_(NR) = C_(BYPASS) = 470 nF

Figure 33. PSRR vs Frequency

V_I– V_O = 0.5 V	C_(OUT) = 10 µF	C_(IN) = 10 µF
	24.09 µV_RMS(C_(NR) = C_(BYPASS) = 100 nF)
	23.54 µV_RMS (C_(NR) = C_(BYPASS) = 470 nF)

Figure 35. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

25.89 µV_RMS(V_O = 1.8 V)	C_(IN) = 10 µF	V_I– V_O = 0.5 V
23.54 µV_RMS (V_O = 2.5 V)	C_(NR) = 470 nF	C_(OUT) = 10 µF
23.54 µV_RMS (V_O = 3.3 V)	C_(BYPASS) = 470 nF

Figure 37. Output Spectral Noise Density vs Frequency (RMS noise (100 Hz to 100 kHz))

Using the same value of C_(NR) and C_(BYPASS) in the X-Axis

Figure 39. Startup Time vs Noise Reduction Capacitance

I_O = 100 mA → 1 A → 100 mA

Figure 41. Load Transient Response

R_L = 33 Ω	C_(NR) = 470 nF	C_(BYPASS) = 470 nF
C_(OUT) = 10 µF	C_(IN) = 10 µF
(1) The internal reference requires approximately 80 ms of rampup time (see Startup) from the enable event; therefore, V_O fully reaches the target output voltage of 3.3 V in 80 ms from startup.

Figure 43. Power-Up and Power-Down Response