Table 9-7 describes several ways how the ultra-low noise floor and PSRR of the device can be improved.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the output voltage noise floor. The LPF is a single-pole filter, and Equation 10 calculates the cutoff frequency. The typical value of R_NR/SS is 250 kΩ. The effect of the C_NR/SS capacitor increases when V_OUT(nom) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, use a 10-nF to 1-µF C_NR/SS.

The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.

A larger C_OUT or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.

Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high-power dissipation across the die increases the output noise because of the increase in junction temperature.

Good PCB layout improves the PSRR and noise performance by providing heat sinking at low frequencies and isolating V_OUT at high frequencies.

Table 9-8 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions with an input voltage of 5.5 V and a load current of 2 A. The 5-V output was chosen as a worst-case nominal operation for output voltage noise.