The output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C_NR/SS). This soft-start eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to the input power bus.

The output voltage (V_OUT) rises proportionally to V_NR/SSduring start-up as the LDO regulates so that the feedback voltage equals the NR/SS voltage (V_FB = V_NR/SS). As such, the time required for V_NR/SS to reach its nominal value determines the rise time of V_OUT (start-up time).

Not using a noise-reduction capacitor on the NR/SS pin can result in output voltage overshoot of approximately 10%. Using a capacitor on the NR/SS pin minimizes the overshoot.