Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated LDO output). Noise can easily be noticed in audio as a hissing or popping sound. Noise produced from an external circuit or the 50- to 60-hertz power-line noise (spikes), along with the harmonics, is an excellent representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry, such as resistors and transistors. The two dominating sources of intrinsic noise are the error amplifier and the internal reference voltage (V_NR/SS). Extrinsic noise, including the switching mode power-supply ac ripple voltage, coupled onto the input supply of the LDO is attenuated by the LDO power-supply rejection ratio, or PSRR. PSRR is a measurement of the noise attenuation from the input to the output of the LDO.

Optimize the intrinsic noise and PSRR by carefully selecting:

• C_NR/SS for the low-frequency range up to the device bandwidth
• C_OUT for the high-frequency range close to and higher than the device bandwidth
• Operating headroom, V_IN – V_OUT (V_DO), mainly for the low-frequency range up to the device bandwidth, but also for higher frequencies to a lesser effect

These behaviors are described in the Typical Characteristics curves.

Figure 8-14 and Figure 8-15 show the measured 10-Hz to 100-kHz RMS noise for a 3.3-V device output voltage with a 0.5-V headroom for different C_NR/SS and C_OUT capacitors and a 1-A load current. Table 8-3 lists the typical output noise for these capacitors.

Figure 8-14 PSRR vs Frequency and I_OUT for V_OUT = 3.3 V, C_OUT = 10 μF

Figure 8-15 PSRR vs Frequency and I_OUT for V_OUT = 3.3 V, C_OUT = 4.7 μF || 4.7 μF|| 1.0 μF

PSRR can be viewed as being simply the ratio of the output capacitor impedance by the LDO output impedance. At low frequency, the output impedance is very low whereas the output impedance of the capacitor is high, resulting in high PSRR. As the frequency increases, the output capacitor impedance reduces and reaches a minima set by the ESR.

As shown in Figure 8-14 and Figure 8-15, and in order to achieve high PSRR at high frequencies, ensure that the output capacitor ESR and ESL are minimal. These figures compare the use of a single 10-μF output capacitor with a 4.7-μF || 4.7-μF || 1.0-μF implementation. Notice that below 200 kHz, there is no impact on performance but above 200 kHz, the PSRR improves by 5 dB to 7 dB.

Minimizing the ESR, ESL generated resonance point in the output capacitance allows for a smoother transition between the LDO active PSRR component to the passive PSRR of the capacitors.