米6体育平台手机版

ZHCSOO0C september 2021 – june 2023 TPS7A94

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

DSC|10

散热焊盘机械数据 (封装 | 引脚)

订购信息

8.1.16 TPS7A94EVM-046 Thermal Analysis

The TPS7A94EVM-046 EVM was used to develop the TPS7A9401DRC thermal model. The DRC package is a 3-mm × 3-mm, 10-pin VQFN with 25-µm plating on each via. The EVM is a 2.85-inch × 3.35-inch (72.39 mm × 85.09 mm) PCB comprised of four layers. Table 8-5 lists the layer stackup for the EVM. Figure 8-19 to Figure 8-23 illustrate the various layer details for the EVM.

Table 8-5 TPS7A94EVM-046 PCB Stackup

LAYER	NAME	MATERIAL	THICKNESS (mil)
1	Top overlay	—	—
2	Top solder	Solder resist	0.4
3	Top layer	Copper	2.8
4	Dielectric 1	FR-4 high Tg	10
5	Mid layer 1	Copper	2.8
6	Dielectric 2	FR-4 high Tg	30
7	Mid layer 2	Copper	2.8
8	Dielectric 3	FR-4 high Tg	10
9	Bottom layer	Copper	2.8
10	Bottom solder	Solder resist	0.4

Figure 8-19 Top Composite View

Figure 8-21 Mid Layer 1 Routing

Figure 8-23 Bottom Layer Routing

Figure 8-20 Top Layer Routing

Figure 8-22 Mid Layer 2 Routing

Figure 8-24 to Figure 8-26 show the thermal gradient on the PCB and device that results when a 1-W power dissipation is used through the pass transistor with a 25°C ambient temperature. Table 8-6 shows thermal simulation data for the TPS7A94EVM-046.

Table 8-6 TPS7A94EVM-046 Thermal Simulation Data

DUT	R_θJA (°C/W)	⍦_JB (°C/W)	⍦_JT (°C/W)
TPS7A94EVM-046	25.6	11.5	0.3

Figure 8-24 TPS7A94EVM-046 3D View

Figure 8-26 TPS7A94EVM-046 Device Thermal Gradient

Figure 8-25 TPS7A94EVM-046 PCB Thermal Gradient