In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 3.3-V clean rail with the spectral noise mask versus frequency shown in Figure 8-29 and a maximum load of 500 mA. The typical 10-μF input and output capacitors and 4.7-μF NR/SS capacitors are used to achieve a good balance between fast start-up time and excellent noise and PSRR performance.

Figure 8-29 Noise Compliance Mask

The output voltage is set using a 22.1-kΩ, thin-film resistor value calculated as described in the Adjustable Operation section. To set the current limit to a value close to the 750 mA required by the application, and to set the PG threshold to 95%, use Table 8-2 to set the R_{FB_PG} top and bottom resistors values at 1.47 MΩ and 100 kΩ, respectively.

Setting R_B to 100 kΩ and using a 4-V V_ON and Equation 1 provide the R_T value of 226 kΩ. V_OFF is calculated with Equation 2 to be 3.5 V.

Figure 8-30 shows that the device meets all design noise requirements except for the noise peaking at 900 kHz. However, this noise peaking can be easily attenuated to the required noise level by means of a pi-filter positioned after the LDO. Figure 8-31 shows that this design is very close to the PSRR level at 1 MHz and can require more margin. Fortunately, both requirements are easily achieved by inserting a pi-filter consisting of a ferrite bead and a small capacitor beyond the LDO and before the load; see Figure 8-28.

The ferrite bead was selected to have a very small dc resistance of less than 50 mΩ, 1 A of current rating, and a relatively small footprint. The added pi-filter components have almost no impact on the LDO accuracy performance and no significant increase in the design total cost.

Figure 8-30 Output Noise vs Frequency

Figure 8-31 PSRR vs Frequency