7.3.1 Short-Circuit and Overcurrent Protection

The TPS7B4254-Q1 device features integrated fault protection, which makes the device ideal for automotive applications. To keep the device in a safe area of operation during certain fault conditions, internal current-limit protection is used to limit the maximum output current. This protection protects the device from excessive power dissipation. For example, during a short-circuit condition on the output, the current through the pass element is limited to I_OUT(LIM) to protect the device from excessive power dissipation.

7.3.2 Integrated Inductive Clamp Protection

During output turnoff, the cable inductance continues to source the current from the output of the device. The device integrates an inductive clamp at the OUT pin to help to dissipate the inductive energy stored in the cable. An internal diode is connected between the OUT and GND pins with a dc-current capability of 600 mA for inductive clamp protection.

7.3.3 OUT Short-to-Battery and Reverse-Polarity Protection

The TPS7B4254-Q1 device can withstand a short to battery on the output, as shown in Figure 22. Therefore, no damage to the device occurs.

Figure 22. OUT Short to Battery, V_IN = V_BAT

A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as shown in Figure 23. In this case, the TPS7B4254-Q1 supply-input voltage is set to 7 V when a short to battery (14 V typical) occurs on the OUT pin, which operates at 5 V. The internal back-to-back PMOS remains on for 1 ms, during which the input voltage of the TPS7B4254-Q1 device charges up to the battery voltage. A diode connected between the output of the dc-dc converter and the input of the TPS7B4254-Q1 device is required in case the other loads connected behind the dc-dc converter cannot withstand the voltage of an automotive battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be eliminated if the output of the dc-dc converter and the loads connected behind it withstand automotive battery voltage.

The internal back-to-back PMOS is switched to OFF when reverse polarity or a short to battery occurs for 1 ms. After that, the reverse current that flows out through the IN pin is less than 10 μA. Meanwhile, a special ESD structure implemented at the input ensures the device can withstand –40 V.

Figure 23. OUT Short to Battery, VIN < V_BAT

In most cases, the output of the TPS7B4254-Q1 device is shorted to the battery through an automotive cable. The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4254-Q1 device when the short to battery occurs. The peak voltage at the output of the TPS7B4254-Q1 device must be lower than the absolute-maximum voltage rating (45 V) during LC oscillation.

7.3.4 Undervoltage Shutdown

The device has an internally fixed undervoltage-shutdown threshold. Undervoltage shutdown activates when the input voltage on IN drops below UVLO. This activation ensures the regulator is not latched into an unknown state during a low input-supply voltage. If the input voltage has a negative transient that drops below the UVLO threshold and then recovers, the regulator shuts down and then powers up with a standard power-up sequence when the input voltage is above the required level.

7.3.5 Thermal Protection

The device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. During continuous normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature exceeds the TSD trip point, the output turns off. When the junction temperature decreases to 15°C (typical) lower than the TSD trip point, the output turns on.

7.3.6 Regulated Output (OUT)

The OUT pin is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has an incorporated soft-start feature to control the initial current through the pass element.

7.3.7 Adjustable Output Voltage (FB and ADJ)

7.3.7.1 OUT Voltage Equal to the Reference Voltage

With the reference voltage applied directly at the ADJ pin and the FB pin connected to the OUT pin, the voltage at the OUT pin equals to the reference voltage at the ADJ pin, as shown in Figure 24.

Equation 1.

Figure 24. OUT Voltage Equal to the Reference Voltage

7.3.7.2 OUT Voltage Higher Than Reference Voltage

By using an external resistor divider connected between the OUT and FB pins, an output voltage higher than reference voltage can be generated as shown in Figure 25. Use Equation 2 to calculate the value of the output voltage. The recommended range for R1 and R2 is from 10 kΩ to 100 kΩ.

Equation 2.

Figure 25. OUT Voltage Higher Than the Reference Voltage

7.3.7.3 Output Voltage Lower Than Reference Voltage

By using an external resistor divider connected at the ADJ pin, an output voltage lower than reference voltage can be generated as shown in Figure 26. Use Equation 3 to calculate the output voltage. The recommended value for both R1 and R2 is less than 100 kΩ.

Equation 3.

Figure 26. OUT Voltage Lower Than the Reference Voltage

7.4.1 Operation With V_IN < 4 V

The maximum UVLO voltage is 3.65 V, and the device generally operates at an input voltage above 4 V. The device can also operate at a lower input voltage; no minimum UVLO voltage is specified. At an input voltage below the actual UVLO voltage, the device does not operate.