Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN – V_OUT) when the pass transistor is fully on. This condition arises when the input voltage falls to the point where the error amplifier must drive the gate of the pass transistor to the rail and has no remaining headroom for the control loop to operate. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage directly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage follows, minus the dropout voltage (V_DO).

In dropout mode, the output voltage is no longer regulated, and transient performance is severely degraded. The device loses PSRR, and load transients can cause large output voltage deviation.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated output current (I_RATED, see the Recommended Operating Conditions table), the dropout voltage for that current scales accordingly. The following equation calculates the R_DS(ON) of the device.