米6体育平台手机版

ZHCST52A September 2023 – November 2023 TPS7B4256-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

D|8
- MSOI002K
DDA|8
- MPDS092F

散热焊盘机械数据 (封装 | 引脚)

DDA|8
- PPTD058I

订购信息

7.2.2.3 Feedforward Capacitor

A feedforward capacitor (C_FF) is recommended to be connected between the OUT pin and the FB pin. C_FF improves transient, noise, and PSRR performance. A higher capacitance C_FF can be used; however, the start-up time increases. For a detailed description of C_FF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

As shown in Figure 7-2, poor layout practices and using long traces at the FB pin results in the formation of a parasitic capacitor (C_FB).

Figure 7-2 Formation of Parasitic Capacitor at the FB Pin

C_FB, along with the feedback resistors R₁ and R₂ can result in the formation of an uncompensated pole in the transfer function of the loop gain. A C_FB value as small as 7 pF can cause the parasitic pole frequency, given by Equation 7, to fall within the bandwidth of the LDO and result in instability.

Equation 7.

f_{P} = \frac{1}{(2 \times π {\times C}_{F B} \times (R_{1} ∥ R_{2}))}

Adding a feedforward capacitor (C_FF), as shown in Figure 7-3, creates a zero in the loop gain transfer function that can compensate for the parasitic pole created by C_FB. Equation 8 and Equation 9 calculate the pole and zero frequencies.

Figure 7-3 Feedforward Capacitor Can Compensate the Effects of the Parasitic Capacitor

Equation 8.

f_{P} = \frac{1}{(2 \times π \times (R_{1} ∥ R_{2}) \times (C_{F F} + C_{F B}))}

Equation 9.

f_{Z} = \frac{1}{(2 \times π \times C_{F F} \times R_{1})}

The C_FF value that makes f_P equal to f_Z, and result in a pole-zero cancellation, depends on the values of C_FB and the feedback resistors used in the application. Alternatively, if the feedforward capacitor is selected so that C_FF ≫ C_FB, then the pole and zero frequencies given by Equation 8 and Equation 9 are related as:

Equation 10.

\frac{f_{p}}{f_{z}} \approx (1 + \frac{R_{1}}{R_{2}}) = \frac{V_{O U T}}{V_{A D J / E N}}

In most applications, particularly where a 3.3-V or 5-V V_OUT is generated, this ratio is not very large, implying that the frequencies are located close to each other and therefore the parasitic pole is compensated. Even for large V_OUT values, where this ratio can be as large as 20, a C_FF value in the range 100 pF ≤ C_FF ≤ 10 nF typically helps prevent instability caused by the parasitic capacitance on the feedback node.

Following good layout practices, as described in the Layout Guidelines section and in the TRKRLDOEVM-119 General-Purpose Tracker LDO Evaluation Module user guide, helps minimize the parasitic feedback pin capacitance to values that prevent the resulting parasitic pole from causing instability.