The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin is a power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold value to the default, V_{(PG_TH)}. When V_OUT exceeds the default power-good threshold, the PG output turns high after the power-good delay period has expired. When V_OUT falls below V_{(PG_TH)} – V_{(PG_HYST)}, the PG output turns low after a short deglitch time.

The power-good threshold is also adjustable from 1.1 V to 5 V by using an external resistor divider between PGADJ and OUT. The threshold can be calculated using Equation 1:

Equation 1.

where

• V_{(PG_ADJ)} is the adjustable power-good threshold
• V_{(PG_REF)} is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 2% accuracy specified under all conditions

By setting the power-good threshold V_{(PG_ADJ)}, when V_OUT exceeds this threshold, the PG output turns high after the power-good delay period has expired. When V_OUT falls below V_{(PG_ADJ)} – V_{(PG_HYST)}, the PG output turns low after a short deglitch time. Figure 7-1 shows typical hardware connections for the PGADJ pin and DELAY pin.

Figure 7-1 Adjustable Power-Good Threshold