ZHCSMK8A December 2020 – April 2021 TPS7B87-Q1
PRODUCTION DATA
Because the power-good (PG) pin is pulled up internally to the output rail, this pin cannot be pulled up to any voltage or wire AND'd like a typical open-drain PG output can be. If this signal must be pulled up to another logic level then an external circuit can be implemented using a PMOS transistor and a pullup resistor. Implementing the circuit shown in Figure 8-7 allows the outputs to be pulled up to any logic rail. If a PMOS transistor is used make sure to pick a transistor with a low threshold voltage as this will determine the output low voltage. this can also be done with a NMOS transistor, but it inverts the logic. This implementation also allows the outputs to be AND'd together like the traditional power-good pins.