SLVSH48A May 2024 – September 2024 TPS7H1121-SP
PRODMIX
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Output Voltage Configuration
- 9.2.2.2 Output Voltage Accuracy
- 9.2.2.3 Enable Threshold
- 9.2.2.4 Soft Start Capacitor
- 9.2.2.5 Programmable Current Limit Resistor
- 9.2.2.6 Characterization of Overcurrent Events that Exceed Thermal Limits
- 9.2.2.7 Power Good Pull Up Resistor
- 9.2.2.8 Capacitors
- 9.2.2.9 Frequency Compensation
- 9.3 Power Supply Recommendations
- 9.4 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
8.3.8 Power Good (PG)
Power Good terminal is an open-drain connection and can be used to sequence multiple LDOs. The PG terminal will be pulled low until the output voltage reaches 95% (typ) of its final level. At that point, the PG pin will be pulled up through the external resistor divider. Since the PG pin is open drain, it can be pulled up to any voltage as long as it does not exceed the recommended maximum of 7V listed in Section 6.5.
Figure 8-1 Sequenced Power Good