ZHCSSO5A July   2023  – October 2023 TPS7H2140-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Current and Voltage Conventions
      2. 8.3.2 Accurate Current Sense
      3. 8.3.3 Adjustable Current Limit
      4. 8.3.4 Inductive-Load Switching-Off Clamp
      5. 8.3.5 Fault Detection and Reporting
        1. 8.3.5.1 Diagnostic Enable Function
        2. 8.3.5.2 Multiplexing of Current Sense
        3. 8.3.5.3 Fault Table
        4. 8.3.5.4 FAULT Reporting
      6. 8.3.6 Full Diagnostics
        1. 8.3.6.1 Short-to-GND and Overload Detection
        2. 8.3.6.2 Open-Load Detection
          1. 8.3.6.2.1 Channel On
          2. 8.3.6.2.2 Channel Off
        3. 8.3.6.3 Short-to-Input Detection
        4. 8.3.6.4 Reverse Polarity Detection
        5. 8.3.6.5 Thermal Fault Detection
          1. 8.3.6.5.1 Thermal Shutdown
      7. 8.3.7 Full Protections
        1. 8.3.7.1 UVLO Protection
        2. 8.3.7.2 Loss-of-GND Protection
        3. 8.3.7.3 Protection for Loss of Power Supply
        4. 8.3.7.4 Reverse-Current Protection
        5. 8.3.7.5 MCU I/O Protection
      8. 8.3.8 Parallel Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 Without a GND Network
        2. 9.4.2.2 With a GND Network
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER STAGE
tON Turn-on delay time VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from ENx rising edge to 10% of VOUTx		 20 50 90 µs
tOFF Turn-off delay time VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from ENx falling edge to 90% of VOUTx		 20 50 90
tRISE Channel turn-on time VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from 50% of ENx to 90% of VOUTx		 66 88 125
tFALL Channel turn-off time VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from 50% of ENx to 10% of VOUTx		 66 88 125
tMATCH tRISE – tFALL VIN = 13.5 V, IOUT = 500 mA.
tRISE is the ENx rising edge to VOUTx = 90%.
tFALL is the ENx falling edge to VOUTx = 10%.		 –50 50
SRON Turn-on slew rate VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from ENx rising edge to 10% of VOUTx		 0.1 0.3 0.55 V/µs
SROFF Turn-off slew rate VIN = 13.5 V, VDIAG_EN = 5 V, IOUTx = 500 mA,
from ENx falling edge to 90% of VOUTx		 0.1 0.3 0.55
CURRENT SENSE
tCS_OFF1 CS settling time from DIAG_EN disabled VIN = 13.5 V, VENx = 5 V, IOUTx = 500 mA. Current Limit = 2 A. From VDIAG_EN falling edge to 10% of VCS. 20 µs
tCS_ON1 CS settling time from DIAG_EN enabled VIN = 13.5 V, VENx = 5 V, IOUTx = 500 mA. Current Limit = 2 A. From VDIAG_EN rising edge to 90% of VCS. 20
tCS_OFF2 CS settling time from IN falling edge VIN = 13.5 V, VENx = 5 V, IOUTx = 500 mA. Current Limit = 2 A. From VENx falling edge to 10% of VCS. 30 100
tCS_ON2 CS settling time from IN rising edge VIN = 13.5 V, VENx = 5 V, IOUTx = 500 mA. Current Limit = 2 A.
From VENx rising edge to 90% of VCS.		 50 150
tMUX Multi-sense transition delay from channel to channel VDIAG_EN = 5V, current sense output delay when multi-sense pins
SEL and SEH transition from channel to channel		 50
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