Figure 8-1 shows how resistor dividers from VIN connected to the EN and OVP pins can be used to set the UVLO and OVP trip voltages. The EN pin controls the ON and OFF state of the internal FET. A voltage at this pin greater than V_IHEN turns on the FET and a voltage less than V_ILEN turns it off. The addition of an external resistor divider from VIN allows the EN pin to configure a different enable rising voltage or an undervoltage monitor (UVLO) based on the V_IHEN and V_ILEN specifications respectively. Typically, applications are optimized to either configure the enable rising voltage or the UVLO threshold. As an example, Equation 1 can be used to calculate the UVLO trip point fixing R_{TOP_EN} = 100 kΩ.

In a similar way to the EN pin, the overvoltage protection (OVP) feature of the device can be configured using a resistor divider from VIN connected to the OVP pin. The trip voltage for the OVP has to be less than the absolute maximum VIN voltage. A voltage at the OVP pin greater than V_OVPR will trip the OVP feature and will turn off the FET and a voltage less than V_OVPF will keep the FET on. If this feature is not desired, the OVP pin should be grounded. Equation 2 can be used to calculated the rising OVP trip point fixing R_{TOP_OVP} = 100 kΩ.

Figure 8-1 UVLO and OVP Thresholds Set by Resistor Dividers

Equation 1.

Equation 2.