ZHCSEJ1 December   2015 TPS7H3301-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VO Sink/Source Regulator
      2. 8.3.2 Reference Input (VDDQSNS)
      3. 8.3.3 Reference Output (VTTREF)
      4. 8.3.4 EN ControL (EN)
      5. 8.3.5 PowerGood Function (PGOOD)
      6. 8.3.6 VO Current Protection
      7. 8.3.7 VIN UVLO Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VIN/VDD Capacitor
        2. 9.2.2.2 VLDO Input Capacitor
        3. 9.2.2.3 VTT Output Capacitor
        4. 9.2.2.4 VTTSNS Connection
        5. 9.2.2.5 Low VIN Applications
        6. 9.2.2.6 S3 and Pseudo-S5 Support
        7. 9.2.2.7 Tracking Startup and Shutdown
        8. 9.2.2.8 Output Tolerance Consideration for VTT DIMM Applications
        9. 9.2.2.9 LDO Design Guidelines
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

HKR Package
16-Pin CFP
Top View - Live Bug
TPS7H3301-SP po_hkr_slvscj5.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VTTREF 1 O Reference output. Connect to GND through 0.1-µF ceramic capacitor.
VDDQSNS 2 I VDDQ sense input. Reference input for VTTREF.
VLDOIN 3 I Supply voltage for the LDO. Connect to VDDQ voltage or an alternate voltage source.
4
5
PGND 6 — Power ground. Connect output for the VTT/ V O LDO to negative pin of the output capacitor.
7
8
EN 9 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.
VDD/VIN 10 I 2.5- or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1 and 10 µF is required.
PGOOD 11 O PGOOD output pin. PGOOD pin is an open drain output to indicate the output voltage is within specification.
VTT/VO 12 O Power output for VTT LDO
13
14
AGND 15 — Signal ground. Connect to negative pin of output capacitors.(1)
VTTSNS 16 I VDDQ sense input, reference input for VTTREF. Voltage sense for VTT/ V O . Connect to positive pin of the output capacitor or the load.
(1) Thermal pad must be connected to GND.
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