ZHCSEJ1 December   2015 TPS7H3301-SP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VO Sink/Source Regulator
      2. 8.3.2 Reference Input (VDDQSNS)
      3. 8.3.3 Reference Output (VTTREF)
      4. 8.3.4 EN ControL (EN)
      5. 8.3.5 PowerGood Function (PGOOD)
      6. 8.3.6 VO Current Protection
      7. 8.3.7 VIN UVLO Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VIN/VDD Capacitor
        2. 9.2.2.2 VLDO Input Capacitor
        3. 9.2.2.3 VTT Output Capacitor
        4. 9.2.2.4 VTTSNS Connection
        5. 9.2.2.5 Low VIN Applications
        6. 9.2.2.6 S3 and Pseudo-S5 Support
        7. 9.2.2.7 Tracking Startup and Shutdown
        8. 9.2.2.8 Output Tolerance Consideration for VTT DIMM Applications
        9. 9.2.2.9 LDO Design Guidelines
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature, unless otherwise noted(1)
MIN MAX UNIT
Input voltage (2) VIN /VDD, VLDOIN, VTTSNS, VDDQSNS –0.36 3.6 V
EN –0.3 6.5
PGND to AGND –0.3 0.3
Output voltage (2) VO /VTT, VTTREF –0.3 3.6 V
PGOOD –0.3 3.6
Peak output current Internally limited A
PG pin sink current 5 mA
TJ Maximum operating junction temperature –55 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground pin unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage VIN / VDD 2.375 3.5 V
Voltage VLDOIN 0.9 3.5
EN, VTTSNS –0.1 3.5
VDDQSNS 1.0 3.5
VO / VTT, PGOOD –0.1 3.5
VTTREF –0.1 1.8
PGND –0.1 0.1
T J Operating junction temperature –55 125 °C

7.4 Thermal Information

THERMAL METRIC (2) (1) (3) TPS7H3301-SP UNIT
HKR (CFP)
16 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(3) Maximum power dissipation may be limited by overcurrent protection.

7.5 Electrical Characteristics

Over full temperature range, –55°C to 125°C, VIN/VDD = 3.3 V and 2.375V,VVLDOIN = 1.8 V, VVDDQSNS = 1.8 V,
VVOSNS/VTTSNS = 0.9 V, VEN = VVIN/VDD, 标准 DDR 应用 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IIN /IVDD Supply current V EN = 3.3 V, No Load 18 30 mA
IVDD(SDN) Shutdown current V EN = 0 V, VDDQSNS = 0, No Load 3 5 mA
V EN = 0 V, VDDQSNS > 0.78 V, No Load 6.5 8
ILDOIN Supply current of VLDOIN V EN = 3.3 V, No Load 575 1200 μA
ILDOIN(SDN) Shutdown current of VLDOIN V EN = 0 V, No Load 50 100 μA
INPUT CURRENT
IVDDQsns Input current, VDDQsns V EN = 3.3 V 4 6 μA
VO / VTT OUTPUT
VVOSNS/VTTSNS Output DC voltage, VO V LDOIN = 2.5 V, VVTTREF = 1.25 V (DDR1), I O = 0 A 1.25 V
–6 6 mV
V LDOIN = 1.8 V, VVTTREF = 0.9 V (DDR2), I O = 0 A 0.9 V
–6 6 mV
V LDOIN = 1.5 V, VVTTREF = 0.75 V (DDR3), I O = 0 A 0.75 V
–6 6 mV
V LDOIN = 1.35 V, VVTTREF = 0.675 V (DDR3L), I O = 0 A 0.675 V
–6 6 mV
V LDOIN = 1.20 V, VVTTREF = 0.60 V (DDR4), I O = 0 A 0.60 V
–6 6 mV
VLODIN – VTT (3) VLODIN > VTT VIN / VDD = 2.95 V, VVDDQSNS = 2.50 V, V TT = VVTTREF – 50 mV (DDR1), I O = 0.5 A 50 230 mV
VIN / VDD = 2.95 V, VVDDQSNS = 2.50 V, V TT = VVTTREF – 50 mV (DDR1), I O = 1 A 101 300
VIN / VDD = 2.95 V, VVDDQSNS = 2.50 V, V TT = VVTTREF – 50 mV (DDR1), I O = 2.0 A(2) 209 400
VIN / VDD = 2.375 V, VVDDQSNS = 1.80 V, V TT = VVTTREF – 50 mV (DDR2), I O = 0.5 A(2) 54 230
VIN / VDD = 2.375 V, VVDDQSNS = 1.80 V, V TT = VVTTREF – 50 mV (DDR2), I O = 1 A(2) 108 300
VIN / VDD = 2.375 V, VVDDQSNS = 1.80 V, V TT = VVTTREF – 50 mV (DDR2), I O = 2.0 A(2) 228 400
VIN / VDD = 2.375 V, VVDDQSNS = 1.50 V, V TT = VVTTREF – 50 mV (DDR3), I O = 0.5 A 52 230
VIN / VDD = 2.375 V, VVDDQSNS = 1.50 V, V TT = VVTTREF – 50 mV (DDR3), I O = 1 A 104 300
VIN / VDD = 2.375 V, VVDDQSNS = 1.50 V, V TT = VVTTREF – 50 mV (DDR3), I O = 2.0 A(2) 216 400
VIN / VDD = 2.375 V, VVDDQSNS = 1.35 V, V TT = VVTTREF – 50 mV (DDR3L), I O = 0.5 A 50 230
VIN / VDD = 2.375 V, VVDDQSNS = 1.35 V, V TT = VVTTREF – 50 mV (DDR3L), I O = 1 A 102 300
VIN / VDD = 2.375 V, VVDDQSNS = 1.35 V, V TT = VVTTREF – 50 mV (DDR3L), I O = 2.0 A(2) 212 400
VIN / VDD = 2.375 V, VVDDQSNS = 1.20 V, V TT = VVTTREF – 50 mV (DDR4), I O = 0.5 A 50 230
VIN / VDD = 2.375 V, VVDDQSNS = 1.20 V, V TT = VVTTREF – 50 mV (DDR4), I O = 1 A 102 300
VIN / VDD = 2.375 V, VVDDQSNS = 1.20 V, V TT = VVTTREF – 50 mV (DDR4), I O = 2.0 A(2) 210 400
VVOTOL/VTTTOL Output voltage tolerance to VVTTREF I VO = –3 A, across VIN voltage range(2) 12 25 34 mV
I VO = 3 A, across VIN voltage range(2) -34 –25 -12
IVOSRCL VO/VTT source current limit With reference to V VTTREF, VVTTSNS = 90% × V VTTREF 3.25 8 A
IVOSNCL VO/VTT sink current limit With reference to V VTTREF, VVTTSNS = 110% × V VTTREF 3.5 5.5 A
RDSCHRG Discharge impedance, Ω V DDQSNS = 0 V, VVO = 0.3 V, V EN = 0 V, TA = 25°C 18 25 Ω
POWERGOOD COMPARATOR
VTH(PG) VO/VTT PGOOD threshold PGOOD window lower threshold with respect to VVTTREF –23.5% –20% –17.5%
PGOOD window upper threshold with respect to VVTTREF 17.5% 20% 23.5%
PGOOD hysteresis 5%
TPGSTUPDLY PGOOD startup delay Startup rising edge, VOSNS within 15% of VVTTREF 2 ms
VPGOODLOW Output low voltage I SINK = 4 mA 0.4 V
TPBADDLY PGOOD bad delay V OSNS is outside of the ±20% PGOOD window 1 μs
IPGOODLK Leakage current V OSNS = VREFIN (PGOOD high impedance),
PGOOD = VIN + 0.2 V 		1 μA
VDDQSNS AND VVTTREF OUTPUT
VDDQSNS VDDQSNS voltage range 1.0 2.80 V
VDDQSNS_UVLO VDDQSNS undervoltage lockout V DDQSNS rising 780 mV
VDDQSNSUVHYS VDDQSNS undervoltage lockout hysteresis 20 mV
V VTTREF VVTTREF voltage VDDQSNS / 2 V
V VTTREF V VTTREF voltage tolerance to VVDDQSNS –10 mA < I VTTREF <10 mA, VVDDQSNS = 2.5 V –15 15 mV
–10 mA <I VTTREF <10 mA, VVDDQSNS = 1.8 V –15 15
–10 mA <I VTTREF <10 mA, VVDDQSNS = 1.5 V –15 15
–10 mA <I VTTREF <10 mA, VVDDQSNS = 1.35 V –15 15
–10 mA <I VTTREF <10 mA, VVDDQSNS = 1.2 V –15 15
I VTTREFSRCL V VTTREF source current limit VTTREF = 0 V 10 40 mA
I VTTREFSNCCL V VTTREF sink current limit VTTREF = 0 V 6 40 mA
I VTTREFDIS VVTTREF discharge current EN = 0 V, V DDQSNS = 0 V, VVTTREF = 0.5 V 1.3 mA
UVLO/EN LOGIC THRESHOLD
VVINUVVIN UVLO threshold Wake up, T A = 25°C 2.18 2.25 V
Hysteresis 50 mV
VENIH High-level input voltage Enable 1.7 V
VENIL Low-level input voltage Enable 0.3
VENYST Hysteresis voltage Enable 0.5
IENLEAK Logic input leakage current EN, T A = 25°C –1 1 μA
THERMAL SHUTDOWN
TSON Thermal shutdown threshold (1) Shutdown temperature 210 °C
Hysteresis 12
(1) Ensured by design, not production tested
(2) Specified by characterization and not production tested
(3) Dropout / Headroom information provided to help designer in optimizing system efficiency

7.6 Typical Characteristics

For Figure 1 through Figure 15, (3 × 150 µF T530D157M010ATE005 tantalum + 4 × 4.7 µF MLCC) or equivalent capacitance/ESR are used on the output.
TPS7H3301-SP D001_SLVSCJ5.gif
VVIN = 3.3 V VDDQSNS = 2.5 V
Figure 1. Output Voltage vs Output Current
TPS7H3301-SP D003_SLVSCJ5.gif
VVIN = 3.3 V VDDQSNS = 1.5 V
Figure 3. Output Voltage vs Output Current
TPS7H3301-SP D005_SLVSCJ5.gif
VVIN = 3.3 V VDDQSNS = 1.2 V
Figure 5. Output Voltage vs Output Current
TPS7H3301-SP D007_SLVSCJ5.gif
VVIN = 2.95 V VDDQSNS = 1.8 V
Figure 7. Output Voltage vs Output Current
TPS7H3301-SP D009_SLVSCJ5.gif
VVIN = 2.375 V VDDQSNS = 1.35 V
Figure 9. Output Voltage vs Output Current
TPS7H3301-SP D011_SLVSCJ5.gif
VDDQSNS = 2.5 V
Figure 11. RF Voltage vs REFOUT Current
TPS7H3301-SP D013_SLVSCJ5.gif
VDDQSNS = 1.5 V
Figure 13. RF Voltage vs REFOUT Current
TPS7H3301-SP D015_SLVSCJ5.gif
VDDQSNS = 1.2 V
Figure 15. RF Voltage vs REFOUT Current
TPS7H3301-SP D017_SLVSCJ5.gif
VIN = 2.375 V VDDQSNS = 1.5 V
Figure 17. Output Voltage vs Output Current, DDR3
TPS7H3301-SP D019_SLVSCJ5.gif
VIN = 2.375 V VDDQSNS = 1.8 V
Figure 19. Output Voltage vs Output Current, DDR2
TPS7H3301-SP D002_SLVSCJ5.gif
VVIN = 3.3 V VDDQSNS = 1.8 V
Figure 2. Output Voltage vs Output Current
TPS7H3301-SP D004_SLVSCJ5.gif
VVIN = 3.3 V VDDQSNS = 1.35 V
Figure 4. Output Voltage vs Output Current
TPS7H3301-SP D006_SLVSCJ5.gif
VVIN = 2.95 V VDDQSNS = 2.5 V
Figure 6. Output Voltage vs Output Current
TPS7H3301-SP D008_SLVSCJ5.gif
VVIN = 2.375 V VDDQSNS = 1.5 V
Figure 8. Output Voltage vs Output Current
TPS7H3301-SP D010_SLVSCJ5.gif
VVIN = 2.375 V VDDQSNS = 1.2 V
Figure 10. Output Voltage vs Output Current
TPS7H3301-SP D012_SLVSCJ5.gif
VDDQSNS = 1.8 V
Figure 12. RF Voltage vs REFOUT Current
TPS7H3301-SP D014_SLVSCJ5.gif
VDDQSNS = 1.35 V
Figure 14. RF Voltage vs REFOUT Current
TPS7H3301-SP D016_SLVSCJ5.gif
VVIN = 3.6 V
Figure 16. Dropout Voltage vs Output Current
TPS7H3301-SP D018_SLVSCJ5.gif
VIN = 3.5 V VDDQSNS = 1.5 V
Figure 18. Output Voltage vs Output Current, DDR3
TPS7H3301-SP D020_SLVSCJ5.gif
VIN = 3.5 V VDDQSNS = 1.8 V
Figure 20. Output Voltage vs Output Current, DDR2
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