ZHCSRP2B February   2023  – December 2023 TPS7H3302-SEP , TPS7H3302-SP

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VDD Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DAP|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

S3 and Pseudo-S5 Support

The TPS7H3302 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both VTTREF and VTT are on when EN = high (S0 state). VTTREF is maintained while VTT is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). Please notice that the EN signal controls only the output buffer for VTT and therefore, while in S3 state, VDDQSNS is present in order to maintain data in volatile memory. As a result, when EN is set high to exit the S3 state, it is desired to bring VTT into regulation as fast as possible. This causes an output current controlled by the current limit of the device and the output capacitors.

When EN = low and the VDDQSNS voltage is less than 0.75 V(typically), TPS7H3302 enters pseudo-S5 state. Both VTT and VTTREF outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4/S5 state). Figure 8-3 shows a typical startup and shutdown timing diagram for an application that uses S3 and pseudo-S5 support.

GUID-20230201-SS0I-G6NW-NF6Z-D4157SMZ5MQ9-low.svg Figure 8-3 Typical Timing Diagram for S3 and Pseudo-S5 Support