The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A C_SS capacitor on the SS/TR pin to GND implements a soft-start time. Equation 5 shows the equation for the nominal soft-start time, t_SS. This is the time it will take VOUT to go from 10% to 90% of the programmed voltage. The voltage reference (VREF) is 0.604 V and the soft-start charge current (I_SS) is 2.5 μA. When calculating the soft-start time t_SS, it is important to take into account the variation of the parameters C_SS, VREF and I_SS as these may cause t_SS to deviate from the nominal value in the actual implementation.

When any of the following four scenarios occur the SS/TR pin is discharged:

• the input UVLO is triggered,
• the EN pin is pulled below 1.05 V,
• the high-side switch current limit threshold is exceeded, or
• a thermal shutdown event occurs

With the exception of the scenario where the high-side current limit threshold is exceeded, the device will then stop switching and enter into low current operation. At the subsequent power-up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft-start behavior.

The device will enter into a pulse-skipping mode during startup in the event that VSENSE is greater than the voltage at the SS/TR pin. During this period, the high-side switch will remain off and the low-side switch will remain on until VSENSE again falls below the voltage at SS/TR.