The performance of any switching converter depends heavily upon the layout of the PCB. Use the following guidelines to design a PCB layout with optimum power conversion performance, EMI performance, and thermal performance.

1. Place ceramic high frequency bypass capacitors as close as possible to the PVIN and PGND pins, which are right next to each other on the package. Place the small value ceramic capacitor closest to the pins. This is very important for EMI performance.
2. Use short and wide traces, or localized IC layer planes, for high current paths, such as V_IN, V_OUT, SW, and GND connections. Short and wide copper traces reduce power loss and noise due to low parasitic resistance and inductance. Wide copper traces also help reduce die temperature, because they also provide wide heat dissipation paths. Use thick copper (2 oz) on high current layer(s) if possible.
3. Confine pulsing current paths (V_IN, SW, and ground return for V_IN) on the device layer as much as possible to prevent switching noises from contaminating other layers.
4. C_BOOT capacitor also contains pulsing current. Place C_BOOT close to the pin and route to SW with short trace. The pinout of the device makes it easy to optimize the C_BOOT placement and routing.
5. Use a solid ground plane at the layer right underneath the device as a noise shielding and heat dissipation path.
6. Place the VCC bypass capacitor close to the VCC pin. Tie the ground pad of the capacitor to the ground plane using a via right next to it.
7. Use via next to AGND pin to the ground plane.
8. Minimize trace length to the FB pin. Both feedback resistors must be located right next to the FB pin. Tie the ground side of R_FBB to the ground plane with a via right next to it. Place C_FF directly in parallel with R_FBT if used.
9. If V_OUT accuracy at the load is important, make sure the V_OUT sense point is made close to the load. Route V_OUT sense to R_FBT through a path away from noisy nodes and preferably on a layer on the other side of the ground plane. If BIAS is connected to V_OUT, do not use the same trace to route V_OUT to BIAS and to R_FBT. BIAS current contains pulsing driver current and it changes with operating mode. Use separated traces for BIAS and V_OUT sense to optimize V_OUT regulation accuracy.
10. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane and the bottom PCB layer. Connect the DAP and NC pins on the short sides of the device to the GND net, so that IC layer ground copper can provide an optimal dog-bone shape heat sink. Heat generated on the die can flow directly from device junction to the DAP then to the copper and spread to the wider copper outside of the device. Try to keep copper area solid on the top and bottom layer around thermal vias on the DAP to optimize heat dissipation.