The TPS7H4010-SEP regulates output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO) level, V_{CC_UVLO}, and the EN voltage is higher than V_{EN_VOUT_H}.

The internal LDO output voltage VCC is turned on when the EN voltage is higher than V_{EN_VCC_H}. The precision enable circuitry is also turned on when VCC is above UVLO. Normal operation of the TPS7H4010-SEP with regulated output voltage is enabled when the EN voltage is greater than V_{EN_VOUT_H}. When the EN voltage is less than V_{EN_VCC_L}, the device is in shutdown mode. The internal dividers make sure V_{EN_VOUT_H} is always higher than V_{EN_VCC_H}.

The EN pin cannot be left floating. The simplest way to enable the operation of the TPS7H4010-SEP is to connect the EN pin to PVIN, which allows self-start-up of the TPS7H4010-SEP when V_IN rises. Use of a pullup resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.

Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 7-5 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.

Figure 7-5 System UVLO

With a selected R_ENT, the R_ENB can be calculated by Equation 10:

Equation 10.

where

• V_{IN_ON_H} is the desired supply voltage threshold to turn on this device

Note that the divider adds to supply quiescent current by V_IN / (R_ENT + R_ENB). Small R_ENT and R_ENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. R_ENT in the hundreds of kΩ range is a good starting point.