The TPS7H4010-SEP is internally compensated. The internal compensation is designed such that the loop response is stable over a wide operating frequency and output voltage range. The internal R-C values are 500 kΩ and 30 pF, respectively.

When large resistance value (MΩ) is used for R_FBT, the pole formed by an internal parasitic capacitor and R_FBT can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for C_OUT, the control loop could have low phase margin. To provide a phase boost an external feed-forward capacitor (C_FF) can be added in parallel with R_FBT. Choose the C_FF capacitor to provide most phase boost at the estimated crossover frequency f_X:

Equation 18.

where

• K = 24.16 with TPS7H4010-SEP

Select C_OUT so that the f_X is no higher than 1/6 of the switching frequency. Typically, f_X / f_SW = 1/10 to 1/8 provides a good combination of stability and performance.

Place the external feed-forward capacitor in parallel with the top resistor divider R_FBT when additional phase boost is needed.

Figure 7-14 Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor C_FF in parallel with R_FBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 19:

An additional pole is also introduced with C_FF at the frequency of:

Select the C_FF so that the bandwidth of the control loop without the C_FF is centered between f_Z-CFF and f_P-CFF. The zero at f_Z-CFF adds phase boost at the crossover frequency and improves transient response. The pole at f_P-CFF helps maintaining proper gain margin at frequency beyond the crossover.

The need of C_FF depends on R_FBT and C_OUT. Typically, choose R_FBT ≤ 100 kΩ. C_FF may not be required, because the internal parasitic pole is at higher frequency. If C_OUT has larger ESR, and ESR zero f_Z-ESR = 1 / (2π × ESR × C_OUT) is low enough to provide phase boost around the crossover frequency, do not use C_FF. Equation 21 was tested for ceramic output capacitors:

Equation 21.

The C_FF creates a time constant with R_FBT that couples in the attenuated output voltage ripple to the FB node. If the C_FF value is too large, it can couple too much ripple to the FB and affect V_OUT regulation. It could also couple too much transient voltage deviation and falsely trigger PGOOD flag.