The TPS7H4010-SEP synchronous switched mode voltage regulator employs fixed frequency peak current mode control with advanced features. The fixed switching frequency is controlled by an internal clock. To get accurate DC load regulation, a voltage feedback loop is implemented to generate peak current command. The HS switch is turned on at the rising edge of the clock. As shown in Figure 7-3, during the HS switch on-time t_ON, the SW pin voltage V_SW swings up to approximately V_IN, and the inductor current I_L increases with a linear slope. The HS switch is turned off when the inductor current reaches the peak current command. During the HS switch off-time t_OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V_SW to swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next clock cycle, before the HS switch is turned on. The regulation loop adjusts the peak current command to maintain a constant output voltage.

Figure 7-3 SW Voltage and Inductor Current Waveforms in CCM

Duty cycle D is defined by the on-time of the HS switch over the switching period:

where

• T_SW = 1 / f_SW is the switching period

In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inverse proportional to the input voltage: D = V_OUT / V_IN.

When the TPS7H4010-SEP is set to operate in auto mode, the LS switch is turned off when its current reaches zero ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is turned on at the next clock cycle.