5.3.1 Finite State Machine (FSM)

The TPS80032 FSM controls boot sequences, TPS80032 state changes and resources initialization. The power sequences are stored in a hard coded table (OTP memory). The FSM reacts on events, which initiates power state transitions.

5.3.2 Hardware Events

• Starting events (going into ACTIVE state):
  • Power on button (PWRON ball)
  • Remote power on (Accessories) (RPWRON ball)
  • Battery plug (VSYS ball)
  • VAC detection (VAC ball)
  • USB VBUS detection (VBUS ball)
  • USB ID detection (USB ID ball)
  • RTC alarm
• Stopping events (going into OFF state):
  • Short PWRON key press (interrupt to the processor that initiates switch off)
  • Long PWRON key press (hardware switch off)
  • Remote power on (RPWRON) (interrupt to processor that initiates switch off)
  • Primary watchdog expire (hardware switch off)
  • Regulator short circuit protection (hardware switch off)
  • Thermal shutdown (hardware switch off)
• Backup events or shutdown events (going into NO SUPPLY or BACKUP state):
  • Removal of main and/or backup battery
  • Low main and/or backup battery

5.3.3 Software Events

• Stopping events (going into OFF state):
  • DEVOFF instruction: DEV_OFF register bit all set to one (PHOENIX_DEV_ON register)
  • Software reset (SW_RESET), going to OFF state and then restart to ACTIVE

5.3.4 Resource Definition

A resource is an element that provides the necessary to a system to operate. Typical resources are supplies, clocks, resets, references, bias. Each resource can be addressed with its unique I²C address RES_ID (Resource Identification).

A remapping of the resource state versus the system state can be done. For example, a resource can be set either ON or OFF when the system state is SLEEP.

5.3.5 Resource Operating Modes

5.3.6 Addressing Resources Registers

Three types of register can be associated to a resource:

• Configuration Registers:
  • CFG_TRANS register
  • CFG_STEP register (DVS resource)
• State Register:
  • CFG_STATE register
• DVS Registers:
  • CFG_FORCE register
  • CFG_VOLTAGE register (DVS resource)

The configuration registers are intended for resource configuration, while state registers are intended to manage the resource state transition; finally DVS registers are intended to dynamic voltage control via DVS-I²C. Configuration and state registers contribute to determine resource behavior. The state register defines to which state the resource has to switch and the timing for the transition. The configuration register defines the resource behavior in a defined state. Although both types of registers can be access by the FSM and the CTL-I²C, it is preferable to reserve I²C access to configuration registers and FSM access to state registers. Access to DVS registers is exclusively done via DVS-I²C in applications using DVS capability.

These registers can be accessed in different ways, individual access to allow accessing registers through their physical address (ID) and broadcast messages that are interpreted by individual resources in function of their configuration

5.3.7 Power Management I/Os Functionality

5.3.8 PREQ1, PREQ2, PREQ3 Hardware Commands

ACTIVE and SLEEP state transitions are transmitted to the TPS80032 device using signal PREQ1. On a PREQ1 transition, the FSM executes an ACTIVE to SLEEP or SLEEP to ACTIVE sequence. This sequence is hardcoded in the OTP memory. FSM conveys sequence information to the resources assigned to PREQ1 (assigned by PREQ1_RES_ASS_X register), by writing in to CFG_STATE register and set each resource in a state based on the state of the PMIC and based on the translation state register setting (XXX_CFG_TRANS). The request signals PREQ2 and PREQ3 are used as enable signals for resources. The regulators and SYSEN, REGEN1, and REGEN2 signals can be assigned to PREQ2 or PREQ3 (PREQ2_RES_ASS_X and PREQ3_RES_ASS_X register), and they are controlled as enabled/disabled with PREQ2 or PREQ3 signals.

If one of the request signal requests the resource, it will be enabled. If none of the request signal requests the resource and the corresponding CFG_STATE register is cleared, it will be disabled.

By default PREQ signals are masked. System state is not affect by PREQ signals while they are masked. PREQ masks configuration bits (MSK_PREQ1, MSK_PREQ2, MSK_PREQ3) are located in the register PHOENIX_MSK_TRANSITION.

PREQ balls status are available in the STS_HW_CONDITIONS register (STS_PREQ1, STS_PREQ2 and STS_PREQ3 bits). PREQ1, PREQ2, PREQ3 are supplied on VIO voltage domain.

The polarity is defined as following:

• High level: resources are in active state
• Low level: resources are in sleep state

Dedicated register bits (SENS_PREQ1, SENS_PREQ2 and SENS_PREQ3) allow reversing the PREQ balls polarity (PHOENIX_SENS_TRANSITION register).

5.3.9 DVS Software Commands

Only SMPS DVS compliant can be accessed by the DVS-I²C.

On top of hardware commands, DVS compliant power resources (SMPS1/2/5) can receive additional commands via the DVS-I²C. The DVS-I²C port can address two types of register:

• A command register
• A voltage register

The DVS command field (2 MSB bits of xxxx_CFG_FORCE register) will be interpreted as follow:

• 00: ON Force Voltage: The power resource is set in ON mode with the voltage value defined in the 6 LSB bits of the command register SMPS1/2/5_CFG_FORCE
• 01: ON: The power resource is set in ON mode with the voltage value defined in the SMPS1/2/5_CFG_VOLTAGE voltage register
• 10: SLEEP Force Voltage: The power resource is set in SLEEP mode with the voltage value defined in the 6 LSB bits of the command register SMPS1/2/5_CFG_FORCE
• 11: SLEEP: The power resource is set in SLEEP mode with the voltage value defined in the SMPS1/2/5_CFG_VOLTAGE voltage register

The SLEEP Force Voltage command with the voltage value set at 000000 must be naturally interpreted as a shutdown command for the power resource.

ON FORCE / SLEEP FORCE set the voltage independently of the adaptive voltage scaling. ON / SLEEP follow the adaptive voltage scaling.

All power resources, LDOs and non-DVS-SMPS, can be accessed by the control I²C (CTL-I²C). The control I²C allows the host processor to access all the internal registers for configuration purpose or resource commands. LDOs state can be changed by writing to the register xxx_CFG_STATE register and the output voltage level can be controlled by xxx_CFG_VOLTAGE register. The five LSBs represent a binary value used to compute the absolute voltage value to be generated by the LDO:

Absolute Voltage value = 1.0 V + 0.1 V * (binary value - 00000001)

This equation applies to all general-purposes LDOs, for all codes from 00000001 to 00011000. For the remaining codes, it has been specified dedicated output voltages:

• 00000000 sets the output voltage to 0 V
• 00011001 to 00011110 codes are reserved
• 00011111 code sets the output voltages at 2.75 V

SMPS state (on/off) can be changed by writing to the register xxx_CFG_STATE register. SMPS_OFFSET and SMPS_MULT are used to control the offset and the extended mode of the SMPS respectively. The output voltage of the SMPS is calculated based on the equations below:

• Offset and Extended mode disabled
  • Nominal Voltage value = 0.6077 V + 0.01266 V * (binary value – 00000001)

• Offset enabled and Extended mode disabled
  • Nominal Voltage value = 0.6077 V + 0.1013 V + 0.01266 V * (binary value – 00000001)

• Offset disabled and Extended mode enabled
  • Nominal Voltage value = (0.6077 V + 0.01266 V * (binary value – 00000001)) * (43/21 + 1)

• Offset and Extended mode enabled
  • Nominal Voltage value = (0.6077 V + 0.1013 V + 0.01266 V * (binary value – 00000001)) * (43/21 + 1)

5.4.1 Warm Reset (NRESWARM)

The TPS80032 device detects a request for a warm reset on the NRESWARM ball. The warm reset restarts the system without turning off the supplies. After a warm reset, the system is configured the same as after a first switch on (default configuration), except that the states of all resources are unchanged and all supply voltage values can be preserved, depending on the warm-reset sensitivity bit value (WR_S bit in SMPSx_CFG_VOLTAGE and LDOx_CFG_VOLTAGE registers):

• All resources not included in the switch-on sequence keep the state (ON or OFF) they have just before the warm reset occurs.
• Depending on the sensitivity bit, those resources either keep the value they had before the warm reset or are set to their default value.
• All resources included in the start-up sequence are always restarted.

During the power-on sequence, the TPS80032 device ignores the warm reset until the host processor releases it.

NRESWARM is an input reset signal. A peripheral or host processor can activate this signal by a software reset. A reset button can be connected to this line to generate a warm reset. The minimum duration of NRESWARM is two clock periods of 32 kHz. The polarity of NRESWARM is active low.

The warm reset affects the POWER and CHARGER registers. Registers for other modules like the USB, FUEL GAUGE, GPADC, and PWM are not affected by a warm reset.

5.4.2 Primary Watchdog Reset

The TPS80032 device includes a primary watchdog timer that generates a reset of the system in case of a software anomaly (no response, infinite loop). The primary watchdog is programmable from 1 to 127 seconds with 1-second steps and a default value of 32 seconds. If the primary watchdog expires, a reset with a new startup is generated. At the same time, the DEVOFF_WDT bit (in the PHOENIX_LAST_TURNOFF_STS register) is set to indicate the primary watchdog expiration. The DEVOFF_WDT bit must be cleared in order to allow a new reset/start-up sequence if a primary watchdog expires again. If the bit has not been cleared the TPS80032 device generates a reset, thus forcing the device to the WAIT-ON/OFF state. This prevents infinite looping in case of software corruption.

The watchdog is initialized to its default value when the system is in the WAIT-ON/OFF state, and starts leaving the WAIT-ON/OFF state to go to the ACTIVE/SLEEP states. The primary watchdog cannot be disabled by I²C writing if it is enabled by the MSK_WDT OTP memory bit.

The HOLD_WDG_INSLEEP bit (in the CFG_INPUT_PUPD1 register) is used to select the states in which the watchdog is running. If the bit is 0, the watchdog is running in the SLEEP and ACTIVE states, whereas if the bit is 1, the watchdog is running in the ACTIVE state and is gated in the SLEEP state.

5.4.3 Thermal Shutdown

If the die temperature gets too high, the thermal shutdown generates a reset, thus forcing the TPS80032 device to the WAIT-ON/OFF state.

5.4.4 NRESPWRON

The NRESPWRON output signal is the reset signal delivered to the host processor at the end of the power-on sequence. It is released when all the TPS80032 supply voltages (core and I/Os) are correctly set up. In addition, the NRESPWRON signal is gated until the 32-kHz crystal oscillator is stable and delivered to the platform. The polarity of the NRESPWRON signal is active low.

5.7.1 Short-Circuit Protection

The short-circuit current limits for all LDOs and SMPS regulators embedded in the TPS80032 device are approximately twice their respective maximum load current. For specific LDO use cases, when the output of the module is shorted to ground, the power dissipation can exceed the power dissipation requirement, if no continuous preventive action is engaged.

The short-circuit protection scheme compares an LDO/SMPS output voltage to a reference voltage and detects a short circuit if the regulator voltage drops slightly below its minimum output voltage (1 V for LDOs and 0.6 V for SMPSs). A short-circuit protection scheme is included in each power resource of the TPS80032 device to ensure that if the output of an LDO or SMPS is short-circuited, the power dissipation does not increase drastically.

All LDOs/SMPSs include this short-circuit protection that monitors the regulator output voltage and generates an interrupt when a short-circuit is detected (see interrupt mapping). The VRTC regulator is the unique power resource that cannot generate an interrupt when shorted. Therefore, this regulator includes a different analog short-circuit mechanism that does not require a switch off the regulator.

If the short-circuit is detected the SMPS_LDO_SHORT_STS register is updated and the application processor needs to clear the short-circuit interrupt (VXXX_SHORT) and turn off the associated power resource within the 10-ms default time. If the interrupt is not cleared before the counter expires, the TPS80032 device switches off automatically. In parallel, the primary watchdog can shut down the device, if the watchdog expires.

In normal use conditions, when the TPS80032 device is turned off, all LDO/SMPS resources (except VRTC/VBRTC) are turned off and their corresponding short-circuit mechanisms are reset. If a short-circuit condition persists in which all power resources should normally be off, the TPS80032 device does not power up again.

5.7.2 SMPS Regulators

The TPS80032 device includes five SMPS regulators, three of which have DVS capability and thus can be selected to provide independent core voltage domains to the host processor. Each SMPS is a high-frequency, synchronous, step-down DC-DC converter allowing the use of low-cost chip inductors and capacitors.

SMPS1 operates with a 3-MHz fixed-switching frequency and the other SMPSs operate at 6-MHz fixed-switching frequency and enters the power-save mode operation at light load currents to maintain high efficiency over the entire load current. Pulse-frequency modulation (PFM) mode extends the battery life by reducing the quiescent current to 30 µA (typical) during light load and standby operation. For noise-sensitive applications, the appropriate SMPS can be forced into fixed-frequency pulse-width modulation (PWM) mode (FORCE PWM setting in SMPSx_CFG_TRANS registers). In shutdown mode, the current consumption is reduced to less than 1 µA.

Each SMPS is a synchronous step-down converter operating with a fixed-frequency, PWM at moderate-to-heavy load currents. At light load currents, the converter operates in power-save mode with PFM. The converter uses a unique frequency locked-ring oscillating modulator to achieve best-in-class load and line response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up, raising the output voltage until the main comparator trips. The control logic then turns off the switch.

One key advantage of the nonlinear architecture is the absence of a traditional feedback loop. The loop response to change in VO is essentially instantaneous, which explains its extraordinary transient response. The absence of a traditional, high-gain compensated linear loop means that the regulator is inherently stable over a wide range of L and CO. Each SMPS integrates a current limit in the P-channel MOSFET (in SMPS1 in the high-side N-channel MOSFET). When the current in the MOSFET reaches its current limit, the MOSFET is turned off and the low-side N-channel MOSFET is turned on for at least 150 ns.

With decreasing load current, the device automatically switches into pulse-skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically, the switching losses are minimized, and the device runs with a minimum quiescent current and maintains high efficiency. The converter positions the DC output voltage approximately 1% above the nominal output voltage. This voltage-positioning feature minimizes voltage drops caused by a sudden load step. When in PFM mode, the converter resumes its operation when the output voltage trips below the nominal voltage. It ramps up the output voltage with a minimum of three pulses and goes into PFM mode when the inductor current has returned to a zero steady state. Because of the dynamic voltage positioning, the average output voltage in PFM mode is slightly higher than its nominal value in PWM mode. During PFM operation, the converter operates only when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into PFM mode when the output voltage exceeds the nominal output voltage.

The rated output current is 5.0/3.0 A for SMPS1, 2.5 A for SMPS2, and 1.1 A for SMPS3, SMPS4, and SMPS5 regulators.

5.7.3 LDO Regulators

All LDOs are integrated so that they can be connected to an internal preregulator, to an external buck boost SMPS, or to another preregulated voltage source.

The output voltages of all LDOs can be selected, regardless of the LDO input voltage level V_IN. There is no hardware protection to prevent software from selecting an improper output voltage if the V_IN minimum level is lower than T_DCOV (total DC output voltage) + D_V (dropout voltage). In such conditions, the output voltage would be lower and nearly equal to the input supply. For example, in further electrical tables, only the possible input supplies, which fulfill the electrical performances on all their range, are mentioned at each selected output.

The regulator output voltage cannot be modified on the fly, from the voltage range of 1.0 to 2.1 V to the other voltage range of 2.2 to 3.3 V and vice versa. The regulator must be restarted in these cases.

If an LDO is not needed and not turned on by software or a switch-on sequence, the external components can be removed. The TPS80032 device is not damaged by this configuration, and the other functions do not depend on the unmounted LDOs and continue to work.

5.9.1 Charger and System Supply Regulator Controller Operation

The operation of the battery charger and the system supply regulator depends on the platform configuration. There are two different configurations for hardware:

• Power Path configuration (POP_APPSCH OTP bit is 1); an external PMOS is needed between VSYS and VBAT.
• Non-Power Path configuration (POP_APPSCH OTP bit is 0); VBAT is used as a system voltage.

In addition, software interaction with battery charging in both configurations depends on the AUTOCHARGE OTP bit:

• Hardware controlled charging (AUTOCHARGE bit is 1); software interaction is minimized.
• Software controlled charging (AUTOCHARGE bit is 0); software controls the battery charging.

The operation in the four different modes has been described in Section 5.9.1.1 through Section 5.9.1.4. The flow chart for startup, shutdown, and fallback (Power Control) operates in parallel with a flow chart of the system supply regulator and battery charging (Charger Control). The safety timer and watchdog operation is described in Section 5.9.6 and the charging profile and default charging parameters are described in Section 5.9.3.

5.9.1.1 Power Path with Hardware Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as the system voltage is above the VSYSMIN_HI threshold level if the device is not already powered on. The hardware starts the system supply regulation and battery charging automatically if a USB Charging Port or VAC Charger is detected, or if the battery voltage is below VBATMIN_HI and the device is powered off. If the VBUS is supplied by the USB standard downstream port and the battery is above VBATMIN_HI or the device is powered on, the system supply regulator and battery charger are not started by hardware. The host processor must enumerate to the USB host, configure to a certain current level, set the VBUS input current limit, and enable the system supply regulator and battery charging.

If the system voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate the fallback situation. A new startup is initiated when the battery is charged above the VBATMIN_HI voltage level and after startup, the host processor clears the bit. If the fallback bit is active during the shutdown, the system supply regulator and battery charging is disabled. This prevents infinite looping in a low/no battery case with a weak charger. The operation is shown in Figure 5-7.

Figure 5-7 Battery Charging Flowchart (With Power Path, AUTOCHARGE=1)

5.9.1.2 Power Path with Software Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as system voltage is above the VSYSMIN_HI threshold level if the device is not already powered on. If the device is powered off, the hardware sets the correct VBUS input current limit and starts the system supply regulator either from VBUS or from VAC and the battery charging using the default values from OTP memory. The default charging voltage must be set to the proper battery threshold voltage level to comply with the USB standard. When the device is powered on, the host processor takes control over charging.

If the system voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate the fallback situation. A new startup is initiated when the battery is charged above the VBATMIN_HI level and the host processor clears the bit. If the fallback bit is active during the shutdown, the system supply regulator and battery charging is disabled. This prevents infinite looping in a low/no battery case with a weak charger. The operation is shown in Figure 5-8.

Figure 5-8 Battery Charging Flowchart (With Power Path, AUTOCHARGE=0)

5.9.1.3 Non-Power Path with Hardware Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as battery voltage is above the VSYSMIN_HI threshold level if the device is not already powered on. The hardware starts the battery charging automatically if USB Charging Port or VAC Charger is detected, or if the battery voltage is below VBATMIN_HI and the device is powered off. If the VBUS is supplied by the USB standard downstream port and the battery voltage is above VBATMIN_HI or the device is powered on, the battery charger is not started by hardware. The host processor must enumerate to the USB host, configure to a certain current level, set the VBUS input current limit, and enable the battery charging.

If the battery voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate about the fallback situation. A new startup is initiated when the battery is charged above the VSYSMIN_HI threshold level and after startup the host processor clears the bit. If the fallback bit is active during shutdown, the battery charging is disabled. This prevents infinite looping in low/no battery case with weak charger. The operation is shown in Figure 5-9.

Figure 5-9 Battery Charging Flowchart (Without Power Path, AUTOCHARGE=1)

5.9.1.4 Non-Power Path with Software Controlled Charging

The TPS80032 device starts up for the VBUS or VAC plug insertion as soon as battery voltage is above the VSYSMIN_HI threshold level if the device is not already powered on. If the device is powered off, the hardware sets the correct VBUS input current limit and starts the battery charging using the default values from OTP memory. The default charging voltage need to be set to good battery threshold voltage level in order to comply with the USB standard. When the device is powered on, the host processor takes control over charging.

If the battery voltage drops below VSYSMIN_LO, the device shuts down and sets a fallback bit to indicate the fallback situation. A new startup is initiated when the battery is charged above the VSYSMIN_HI threshold level and the host processor clears the bit. If the fallback bit is active during the shutdown, the battery charging is disabled. This prevents infinite looping in a low/no battery case with a weak charger. The operation is shown in Figure 5-10.

Figure 5-10 Battery Charging Flowchart (Without Power Path, AUTOCHARGE=0)

5.9.2 System Supply Regulator

During software-controlled charging, software selects the VBUS input current limit, the VBUS input voltage collapse level, and the system supply regulation voltage. The programmable resources are:

• Input limit current set point register CIN_LIMIT[3:0] (maximum current drawn from VBUS charging source)
• Input voltage set point register BUCK_VTH[2:0] (VBUS voltage collapsing level)
• System supply voltage set point register

The system supply regulation voltage can be a fixed voltage or follow the battery voltage allowing the linear battery charger to regulate the charging current and voltage (DPPM control mode).

5.9.3 Battery Charging

5.9.3.1 Power Path Configuration

When the Power Path configuration is used, the battery charging consists of two different regulators, the system supply regulator generating the system supply (VSYS) from the USB VBUS voltage and a linear battery charging loop regulating the battery node (VBAT) from the system supply (VSYS) using an external PMOS transistor. During the preconditioning phase, an integrated current source is used for battery charging. The use of the dedicated loop for battery charging allows monitoring of the battery current and voltage independently and minimizes the power dissipation thanks to the low-ohmic external transistor.

The TPS80032 device includes five analog loops that influence the system supply regulator's output current:

• System voltage regulation loop, maintaining the system voltage (VSYS) at constant level (VSYS_PC) during preconditioning and precharging and at (VBAT+DLIN[1:0]) level during full-charge phase and end-of-charge phase.
• VBUS voltage anticollapse loop sensing the VBUS voltage and preventing the VBUS voltage from dropping below the programmed level (BUCK_VTH[2:0]).
• VBUS input current loop sensing the input current and limiting it below the programmed level (CIN_LIMIT[5:0]).
• Thermal regulation loop sensing the DCDC temperature and limiting it below thermal shutdown level.
• Cycle-by-cycle current monitoring loop sensing the current in high-side switch and limiting it below cycle-by-cycle limit (BUCK_HSLIMI).

The dedicated battery charging control includes three loops that influence the battery charging current:

• Constant current (CC) loop sensing the battery current and limiting it below charging current level (VICHRG[3:0]).
• Constant voltage (CV) loop sensing the battery voltage and limiting it below charging voltage level (VOREG[5:0]).
• DPPM loop monitoring the voltage between system voltage and battery voltage and limiting the voltage to threshold level (DLIN[1:0]/2) by decreasing the charging current.

Figure 5-11 shows the control loops for the system supply regulation and for the battery charging.

Figure 5-11 System Supply Regulator and Battery Charging Control Loops

CAUTION

Resistor R2 is used for charging current control in Power Path configuration and must be placed even if Gas Gauge is not used.

In addition, a battery current is monitored and if the termination current level (VITERM[2:0]) is detected an interrupt is generated and battery charging is stopped according to the selected operation.

The battery charging profile consists of three phases:

• Preconditioning
• Precharging
• Full-charge phase

NOTE

The DLIN[1:0] voltage level must be selected so that the voltage is higher than the maximum dropout on the switch (maximum charging current multiplied by the maximum resistance of the switch).

Figure 5-12 shows a charging profile and the different parameters programmed in OTP memory and software programmable parameters for charging with Power Path. The charging current is usually limited by the VBUS input current loop when charging from the standard downstream port because the limit is set to 100 or 500 mA. If the charging source cannot provide the current the charger is drawing, the VBUS voltage decreases. The VBUS anticollapse loop senses the VBUS voltage and decreases the current so that the voltage does not fall below the programmed voltage level (see Section 5.9.4).

Figure 5-12 Battery Charging Profile with Power Path (Resistor R2 = 20 mΩ)

5.9.3.2 Non-Power Path Configuration

When the non-Power Path configuration is used, the battery charging is controlled by switched-mode regulator from the USB VBUS voltage.

The TPS80032 device includes six analog loops that influence the output current:

• VBUS voltage anticollapse loop sensing the VBUS voltage and preventing the VBUS voltage from dropping below the programmed level (BUCK_VTH[2:0]).
• VBUS input current loop sensing the input current and limiting it below the programmed level (CIN_LIMIT[5:0]).
• Constant voltage (CV) loop sensing the battery voltage and limiting it below charging voltage level (VOREG[5:0]).
• Constant current (CC) loop sensing the battery current and limiting it below charging current level (VICHRG[3:0]).
• Cycle-by-cycle current monitoring loop sensing the current in high-side switch and limiting it below cycle-by-cycle limit (BUCK_HSLIMI).
• Thermal regulation loop sensing the DCDC temperature and limiting it below thermal shutdown level.

Figure 5-13 shows the control loops for the battery charging.

Figure 5-13 Battery Charging Control Loops.

In addition, a battery current is monitored and if the termination current level (VITERM[2:0]) is detected an interrupt is generated and battery charging is stopped according to the selected operation.

The battery charging profile consists of three phases:

• Preconditioning
• Precharging
• Full-charge phase

Figure 5-14 shows a charging profile and the different parameters programmed in OTP memory and software programmable parameters for HW controlled operation (AUTOCHARGE=1) and Figure 5-15 shows a charging profile and the different parameters programmed in OTP memory and software programmable parameters for SW controlled operation (AUTOCHARGE=0). The charging current is usually limited by the VBUS input current loop when charging from the standard downstream port because the limit is set to 100 or 500 mA. If the charging source cannot provide the current the charger is drawing, the VBUS voltage decreases. The VBUS anticollapse loop senses the VBUS voltage and decreases the current so that the voltage does not fall below the programmed voltage level (see Section 5.9.4).

Figure 5-14 Battery Charging Profile Without Power Path (AUTOCHARGE=1, Resistor R9 = 68 mΩ)

Figure 5-15 Battery Charging Profile Without Power Path (AUTOCHARGE=0, Resistor R9 = 68 mΩ)

5.9.4 Anticollapse Loop and Supplement Mode

There are two different anticollapsing loops; one monitoring the VBUS input and controlling the switched-mode regulator and another one with Power Path operation (DPPM) monitoring the VSYS line and controlling the linear battery charger loop.

The anticollapse loop of the VBUS input operates so that the VBUS input voltage is monitored continuously and the current of the switched-mode regulator is controlled by an analog loop to maintain the defined VBUS input voltage (programmed with the BUCK_VTH[2:0] bits in the ANTICOLLAPSE_CTRL1 register). If the VBUS source cannot deliver high enough current and the VBUS voltage drops, the VBUS input current is decreased by the analog loop so that the VBUS voltage stays at programmed level. If an external PMOS is used to protect the VBUS input against negative voltage, then the VBUS voltage at the connector can be slightly different because the anticollapse loop monitors the voltage at the PMIC input.

The anticollapse loop of the linear battery charger (DPPM) monitors the system voltage (VSYS) and controls the battery charging current. If battery voltage is below the VBATMIN_HI the threshold, the level for the DPPM loop is 3.4 V, whereas if the battery voltage is above VBATMIN_HI, the VSYS voltage tracks the VBAT voltage and the DPPM threshold is 50% of the programmed tracking voltage.

Figure 5-16 shows an example of DPPM loop and supplement mode operation. The charging current is set to 1 A and the VBUS input current limit is 1.5 A. When the system load is small the 1000 mA charging current can be generated with around 750 mA VBUS current, thanks to the efficient DCDC converter. If the system load is increased to around 900 mA level, the 1500 mA VBUS input current limit is reached and the DPPM loop decreases the battery charging current in order to maintain 50% of the programmed tracking voltage across the external FET. If the system load is increased further up to around 1900 mA level, the battery charging current decreases to 0 mA and the supplement mode is enabled. Increasing the system load above 1900 mA level directly affects the battery discharge current level. When the system load is decreased the operation is opposite entering from supplement mode into DPPM loop operation and finally out from VBUS input current limit mode.

Figure 5-16 Example of DPPM Loop and Supplement Mode Operation (V_VBUS = 5 V, V_BAT = 3.5 V, 1.5 A VBUS Input Current Limit)

5.9.5 Battery Temperature Monitoring

JEITA requirements define the maximum battery charging current and voltage at different temperature ranges for Li-Ion batteries. The TPS80032 device supports the JEITA requirements with hardware-based temperature measurement gating the battery charging below and above the preset temperature values (typically 0°C and 60°C). Between these limits host processor must monitor the battery temperature using the integrated general-purpose analog-to-digital converter (GPADC) and setting the charging current and voltage accordingly. Figure 5-17 shows the voltage and current limits at different temperatures.

Figure 5-17 Charging Current and Voltage Limits at Different Temperatures

Figure 5-17 allows two options for charging between 0°C and 10°C. As shown in the figure, #1 allows charging up to 4.10 V with 1C current and #2 allows charging up to 4.25 V with 0.5C current. The term 1C defines the charging current related to the battery capacity. For a 1200-mA-h battery 1C corresponds to a 1.2-A current.

The battery temperature is measured using an external NTC resistor. The measurement is enabled before the charging starts and the temperature is constantly monitored during charging. If the battery temperature is outside of the valid range, the charging is gated; if the temperature returns to the valid range, the charging continues. In Power Path mode the system supply regulation is continued when the battery charging is gated. The gating of the charging can be disabled with an OTP memory bit (EN_BAT_TEMP) if needed. The temperature measurement circuitry is enabled if VBUS or an external charger is detected. An interrupt (CHRG_CTRL) is always generated when the battery temperature crosses the temperature limits in both directions. The interrupt generation can be masked if needed.

Figure 5-18 shows the battery temperature measurement circuitry.

Figure 5-18 Battery Temperature Measurement

Because the NTC characteristics are highly nonlinear, it is combined with two resistors allowing linearization of its characteristics and making the sensitivity of the system more constant over a wide temperature range. The resulting voltage at GPADC_IN1 can be measured using the GPADC and is also monitored by two comparators that enable the charge of the battery only when the temperature is within a specified window, typically 0°C to 60°C. Resistors R_X and R_Y are used to set the desired temperature threshold levels.

5.9.6 Safety Timer and Charging Watchdog

The TPS80032 device includes a safety timer, the timing of which depends on the charging control mode and the USB Charging Port detection result. During hardware-controlled charging, the period for the USB charging port and the USB standard downstream port is approximately 6 minutes; for customer-specific chargers, this period is approximately 14 minutes. Longer values can be selected with the OTP memory (CHWDT_DEP0 bit), 11 minutes instead of 6 minutes and 29 minutes instead of 14 minutes. Charger source dependency on the timer values can be enabled and disabled by OTP memory (CHWDT_DEP_DETN bit). If disabled, the timer value is always set as for the USB standard downstream port and for the customer-specific charger (longer timer value). During software-controlled charging the safety timer is replaced by charging watchdog (SW WDT), host processor can select the watchdog time up to 127 seconds. The transition from safety timer to software-controlled watchdog occurs when software updates the WDG_RST, WDT[6:0], VICHRG[3:0], VOREG[5:0] bits or CONTROLLER_CTRL1 register. The different safety timer and watchdog times are summarized in the EPROM bits Application Note. If the AUTOCHARGE mode is selected by OTP memory bit, the fixed 8-hour watchdog (HW WDT) is taken into use when the battery voltage is above the VBATMIN_HI level.

If the safety timer or watchdog expires, the battery charging is gated and interrupt is sent to host processor. In Power Path configuration, the system supply regulator still continues to operate when the battery charging is gated.

The operation of the safety timer and watchdog is presented in Figure 5-19.

Figure 5-19 Safety Timer and Charging Watchdog

5.9.7 Limit Registers

During the full-charge phase, host processor sets the charging voltage and current. However, the device limits the current and voltage to a level that is defined in the limit registers (CHARGERUSB_CTRLLIMIT1 and CHARGERUSB_CTRLLIMIT2). The limit registers in the device must be written just after the startup. Host processor must check the battery type and define the maximum charging current and voltage for the battery being used, write the limit values, and lock the limit registers with the LOCK_LIMIT bit, so that these cannot be changed when the device is powered on. This ensures that third-party software or a virus cannot set a charging current or voltage that is too high. The limit values are reset during power off by the NRESPWRON signal and they must be written by host processor during every power up. Figure 5-20 shows the structure of the limit and programming registers.

Figure 5-20 Charging Current and Voltage Limit Registers

5.9.8 Battery Presence Detector

The TPS80032 device supports battery detection. The presence of the battery can be detected with the GPADC_IN0 input signal. The interface has two different functions:

• Detect battery removal and presence
• Measure the size of the resistor connected to the GPADC_IN0 line in the battery pack using the GPADC

Battery pack removal is detected by a comparator that monitors GPADC_IN0. The battery pack must have a pull-down resistor (R_BRI) and the device has a current source (I_BRI) in the line. If the battery pack is removed, GPADC_IN0 rises above the comparator threshold level, the battery removal is detected, and the device sends an indication (BAT interrupt) to the host processor. In addition, battery charging is terminated if the battery is not present. Battery removal is detected with a comparator and a current source supplied on the VRTC supply domain. This supply scheme allows detection in a dead battery case configuration, because the VRTC can be supplied from the VBUS or VAC lines. The battery presence detection module is enabled during the charging and during the ACTIVE and SLEEP states.

Figure 5-21 shows a block diagram of the battery presence detection circuitry.

Figure 5-21 Battery Presence Detector

5.9.9 Indicator LED Driver

The device has an indicator LED driver that indicates charging is ongoing during hardware-controlled charging. During hardware-controlled charging, the LED driver is enabled only if the charging is ongoing and it is turned off if the battery is not charged. The supply for the charging indicator LED driver is generated from CHRG_PMID or VAC, depending on the active charging path. The CHRG_PMID pin is used instead of the VBUS line so that the LED indicator current is included into the VBUS input current limit.

During power on, host processor can control the indicator LED regardless of the charging with register bits (LED_PWM_CTRL1 and LED_PWM_CTRL2). The supply for the LED can be selected as CHRG_PMID, VAC, or CHRG_LED_IN. The current level can also be selected and the dimming function can be used. Dimming is done with a 128-Hz PWM signal, which has 255 linear steps. The LED output pin has a selectable pulldown when the module is disabled; the pulldown is enabled by default.

The indicator LED driver is also used to indicate if the device cannot power on after a key press (PWRON). If the battery voltage is too low for startup, the LED driver gives three 300-ms pulses with a 300-ms duration between the pulses.

5.9.10 Supported Charging Sources

The following chargers are supported with the integrated switched-mode charger from the USB connector:

• Dedicated Charging Port (DCP)
• Charging Downstream Port (CDP)
• Standard Downstream Port (SDP)
• Chinese charger

To configure the system supply regulator and charger for proper operation mode depending on the charging source characteristics, the charging source type must be detected and identified. The detection of the charger attached to the USB connector is made inside the device by detecting a voltage greater than VINmin on the charger input.

To minimize the capacitance of the data lines, the type of the charger connected to the USB connector can be identified by the USB PHY and the information of the maximum current drawn from the charging source can be transmitted to the device with a dedicated signal (CHRG_DET_N). The TPS80032 device enables detection by delivering the LDOUSB supply (selectable by OTP memory bit, AUTO_LDOUSB_DIS). The charger detection circuitry must deliver at least a 1.8-V voltage level to the CHRG_DET_N input pin, by default a high logic level indicating that a USB charging port is detected. The polarity of the charger detection signal can be selected with an OTP memory (DET_N_POL bit). The accessory charger adapter (ACA) is identified in the TPS80032 device. A typical connection of the PMIC and USB PHY is shown in Figure 5-22.

Figure 5-22 Connection for the USB Charging Port Detection

The device can be interfaced with an ACA (external to the terminal) to support charging from the USB Charging Port and USB communication to other USB devices from the USB port. For a description of ACA detection, see USB OTG, USB OTG.

5.9.11 USB Suspend

The TPS80032 device includes a HZ_MODE bit which is usable, for example during USB suspend periods. The benefit of the bit is that it can be used to gate the charging without changing any charging parameters. When the suspend period ends, clearing the bit continues the battery charging.

5.9.12 Support for External Charging IC

The TPS80032 device can be interfaced with an auxiliary stand-alone charger device to support the following use cases:

• Simultaneous battery charging from other than USB connector (different connector) and OTG operating mode with USB connector (the integrated switched-mode system supply regulator used as the VBUS supply)
• System supply generation and charging from the sources not connected to the USB connector

In the Power Path configuration the battery charging is always controlled by the TPS80032 device and the external IC only generates the system supply which is needed for the battery charging. In the non-Power Path configuration the external IC is used for battery charging. Figure 5-23 shows the connections between TPS80032 device, application processor and external charging IC (BQ24159) in Power Path configuration.

Figure 5-23 Connection Diagram for External Charging Interface in Power Path Configuration

The external IC is enabled with a 1.8-V CMOS level signal, CHRG_EXTCHRG_ENZ. A low logic level indicates that the regulator is enabled. The system supply regulation / battery charging status is indicated with the CHRG_EXTCHRG_STATZ signal. An external IC pulls the signal down during operation.

The integrated USB regulator can be associated with an external VAC regulator. For that reason, the VAC wall charger input is connected to the device to define the priorities. These priorities are controlled by hardware when the device is powered off (NRESPWRON=0):

• When the VBUS is detected and the VAC is not detected, the USB input is used.
• When the VAC is detected and the VBUS is not detected, the external charging input (VAC) is used.
• When the VBUS and VAC are detected:
  • If CHRG_DET_N = 0 and ACA (RID_A, RID_B or RID_C) is not detected (100-mA VBUS input current limit), the VAC wall charger is expected to be better (or equivalent) and thus is chosen as the default input path.
  • If CHRG_DET_N = 1 or ACA (RID_A, RID_B or RID_C) is detected (USB Charging Port detected), the USB is expected to be sufficient for system supply generation and charging and thus is chosen as the default input path.

If there is a fault condition on a charger during hardware-controlled operation and the fault condition continues for at least 2.5 seconds, the input source is changed for a lower priority input. The change into a lower priority input only prevents infinite looping between inputs. If only one charger is attached, the regulator is not disabled in a fault condition, and if the fault condition does not disappear; the input is terminated when the watchdog expires.

5.9.13 Battery Charger Interrupts

Figure 5-24 shows the system supply regulator and battery charger interrupt handling structure.

Figure 5-24 Interrupt Generation Architecture

When the INT interrupt signal is set, host processor must read the reason of the interrupt by reading the three interrupt status registers (INT_STS_A, INT_STS_B, and INT_STS_C). The battery charging related register bits (CHRG_CTRL, EXT_CHRG, and INT_CHRG) are in the INT_STS_C register. The source of the interrupt is

• CHRG_CTRL: The interrupt source is in the charger controller.
• EXT_CHRG: The interrupt source is in external charging IC.
• INT_CHRG: The interrupt source is in the TPS80032 battery charger.

The CHRG_CTRL indication can be further identified from the CONTROLLER_STAT1 register. This register shows the actual status of the different interrupt sources, so if the situation disappears before software can read it, software cannot know the real reason for the interrupt.

The origin of the external charger interrupt must be read from the external charging IC. The CHRG_EXTCHRG_STATZ bit shows the actual level of the status signal.

The source for the INT_CHRG interrupt must be further clarified in the CHARGERUSB_INT_STATUS register, which stores the latched information. The bits in the CHARGERUSB_INT_STATUS register are cleared by read access.

As an example, if the battery temperature goes above threshold level the BAT_TEMP_OVRANGE bit in CONTROLLER_STAT1 register is high. This sets LINCH_GATED bit in CONTROLLER_STAT1 register to high which sets CHRG_CTRL interrupt bit high and sets INT line low. Host processor detects the interrupt and reads INT_STS_A, INT_STS_B, INT_STS_C, CONTROLLER_STAT1 and LINEAR_CHRG_STS registers and finds the reason for the interrupt.

5.10.1 ID Line

The USB Battery Charging Specification describes the operation of the ACA. The RID_A, RID_B, and RID_C resistors are related only to the different ACA operations, whereas the grounded and floating IDs (ROTG_A, ROTG_B = RID_FLOAT) are related to the connections of the USB OTG standard plugs (See "Battery Charging Specification, Revision 1.2"). When either of the RID_A, RID_B, or RID_C resistance is in place, the VBUS is delivered by the ACA. This allows the device to wake up from VBUS or ID. The host can then enable the ID active comparators by writing ID_ACT_COMP bit (in USB_ID_CTRL_SET register) to correctly identify the different RID values. In addition, an interrupt is generated if the resistance on the ID ball is changing.

During hardware-controlled charging, the TPS80032 device monitors if an ACA is connected and sets the corresponding VBUS input current limit.

The following pullup and pulldown resistors and current sources can be connected to the ID line:

• ID_PU_220K bit enables an ID 220-kΩ pullup to the LDOUSB supply.
• ID_PU_100K bit enables an ID 100-kΩ pullup to the LDOUSB supply.
• ID_GND_DRV bit enables an ID 10-kΩ pulldown.
• ID_SRC_16U bit enables an ID 16-µA current source on the LDOUSB supply.
• ID_SRC_5U bit enables an ID 5-µA current source on the LDOUSB supply.
• ID_WK_UP_COMP enables an ID 9-µA current source (IID_WK_SRC) on the VRTC supply.

The ID wake-up comparator is used when the TPS80032 device is in the WAIT-ON or SLEEP state. It allows start up of the TPS80032 device when a USB cable A-plug is attached (A-plug has a pulldown resistor, ROTG_A, to ground on the ID line).

Four comparators, supplied on the LDOUSB regulator, are implemented to evaluate the proper external ID resistor. Additional logic between those comparators allows the detection of the five debounced interrupts (fixed 30-ms debouncing):

• ID_FLOAT
• ID_A
• ID_B
• ID_C
• ID_GND

It is possible to use the GPADC to monitor the voltage on the ID line (channel 14). A 6.875-V maximum voltage on the ID line corresponds to a 1.25-V maximum dynamic at the input stage of the GPADC converter, allowing a 6.0-V maximum measurement.

Figure 5-25 shows the block diagram of the ID resistance detection and the decoding.Table 5-1 lists the ID resistance interrupt decoding.

Figure 5-25 ID Resistance Detection

5.10.2 VBUS Line

The VBUS wake-up comparator is used when the TPS80032 device is in the PRECHARGE, WAIT-ON, SLEEP, or ACTIVE state. It allows startup of the TPS80032 device when a USB cable plug is attached with a VBUS voltage level of 3.6 V minimum being present on the VBUS line.

The LDOUSB regulator, the ACA comparators and 16-µA current source can be selected to be controlled by the VBUS wake-up comparator until the first I²C write access to the LDOUSB resource state register (LDOUSB_CFG_STATE) (by setting the AUTO_LDOUSB_DIS OTP bit to 0).

The following pullup and pulldown resistors and current sinks/sources can be connected to the VBUS line:

• VBUS_CHRG_VBAT bit enables a VBUS 2-kΩ pullup to the VSYS supply.
• VBUS_CHRG_PMID bit enables a VBUS 2-kΩ pullup to the CHRG_PMID supply.
• VBUS_DISCHRG bit enables a VBUS 10-kΩ pulldown.
• VBUS_IADP_SRC bit enables a VBUS 1.4-mA current source on the VANA supply.
• VBUS_IADP_SINK bit enables a VBUS 1.5-mA current sink.
• RA_BUS_IN resistor is fixed and a combination of all parallel resistor bridges implemented on VBUS in the various IPs such as backup battery, OTG, and charger.
• RVBUS_LKG represents the TPS80032 device internal leakage.

Related to the OTG 1.3 revision, four comparators supplied on the VANA regulator are implemented to evaluate the proper voltage level on the VBUS line.

In the OTG 2.0 revision, only one comparator is required for the session valid detection (VOTG_SESS_VLD) supplied also on the VANA domain. Still, the VA_VBUS_VLD comparator can be used to detect a possible VBUS short-circuit condition.

The TPS80032 device embeds the OTG 2.0 optional features related to the VBUS ADP probing and sensing, and hence with two additional comparators supplied on VANA (VADP_PRB and VADP_SNS).

Seven comparators allow the detection of the four OTG 1.3 and the three OTG 2.0 debounced interrupts:

• VA_VBUS_VLD (OTG 1.3/OTG 2.0) – fixed 30-ms debouncing
• VB_SESS_VLD (OTG 1.3) – fixed 30-ms debouncing
• VA_SESS_VLD (OTG 1.3) – fixed 30-ms debouncing
• VB_SESS_END (OTG 1.3) – fixed 30-ms debouncing
• VOTG_SESS_VLD (OTG 2.0) – fixed 30-ms debouncing
• VADP_PRB (OTG 2.0) – fixed 2x 30-µs debouncing
• VADP_SNS (OTG 2.0) – fixed 2x 30-µs debouncing

It is possible to use the GPADC to monitor the voltage on the VBUS line (channel 10), see GENERAL-PURPOSE ADC for more information.

5.10.3 ADP on VBUS Line

The ADP lets the device detect when a remote device is attached or detached with a low power consumption. The ADP detects the change in the VBUS capacitance that occurs when two devices are attached or detached. The capacitance is detected by first discharging (VBUS_IADP_SINK) the VBUS line and then measuring the time it takes for VBUS to charge to a VADP_PRB voltage level with a VBUS_IADP_SRC current source. The change in the capacitance is detected by looking for a change in the T_ADP_RISE charge time. This procedure is called ADP probing.

If an A-device is attached to a B-device, and both support ADP features, the A-device performs ADP probing and the B-device performs ADP sensing. During ADP sensing, the B-device looks for ADP probing activity on the VBUS line. If ADP probing activity is detected, the B-device determines that the A-device is still attached.

As shown in Figure 5-26, the ADP module has timing register bits (T_ADP_HIGH, T_ADP_LOW, and T_ADP_RISE), control logic, a current source (VBUS_IADP_SRC), a current sink (VBUS_IADP_SINK), and two comparators (VADP_PRB [ADP probing] and VADP_SNS [ADP sensing]).

Figure 5-26 Attach Detection Protocol Scheme

Figure 5-27 shows the ADP timing diagram.

Figure 5-27 ADP Timing Diagram

The limit registers (T_ADP_LOW[7:0] and T_ADP_HIGH[7:0]) and the last measurement time (T_ADP_RISE[7:0]) are reset when the digital module is disabled.

During the ADP sensing mode, the VADP_SNS comparator is used. The digital module monitors the comparator output to ensure that it toggles and the time duration between the rising edge of the comparator output signal is shorter than T_ADP_SNS. If there is no new rising edge within the T_ADP_SNS period, the module generates an ADP interrupt.

Figure 5-28 shows the ADP sensing timing diagram.

Figure 5-28 ADP Sensing Timing Diagram

During ADP probing, the VADP_PRB comparator is used. The time interval measurement counter is reset and the VBUS_IADP_SINK current sink is turned on for T_ADP_SINK. The T_ADP_SINK time is long enough to discharge the VBUS voltage below VADP_DSCHG. There is no comparator to monitor the discharge level. After that, the current sink is turned off, the current source VBUS_IADP_SRC is turned on, and the time interval measurement counter starts to count 32.768-kHz crystal clock cycles. When the VBUS voltage reaches VADP_PRB voltage level the current source is turned off, and the time interval measurement counter is stopped. If the VADP_PRB voltage is not reached before counter value is 255, the counter value is stopped to 255. The current source is disabled when the voltage reaches VADP_PRB level or the next current sink period starts. If the measured time interval value is lower than T_ADP_LOW[7:0] or higher than T_ADP_HIGH[7:0], an interrupt is generated. The host processor sets the limit values so that the operation fulfills the requirements of the OTG 2.0 specification. Figure 5-29 shows the ADP probing timing diagram.

Figure 5-29 ADP Probing Timing Diagram

5.11.1 Autocalibration

Autocalibration is enabled by host. During autocalibration, the gas gauge performs eight measurements so that the inputs for the ADC are short-circuited. The result indicates the offset error of the gas gauge. The result is stored in the CC_OFFSET[9:0] bits and the completion of the measurement procedure is indicated with the CC_AUTOCAL interrupt. Software must read the offset error result (CC_OFFSET[9:0] bits in FG_REG_08 and FG_REG_09 registers) and use that to compensate the actual measurement results. The CC_CAL_EN bit self-clears when the calibration completes. The gas gauge must be enabled (FGS bit TOGGLE1 register) before starting the calibration. The temperature variation changes the offset error, so the recalibration is preferred during operation.

5.11.2 Auto-Clear and Pause

The auto-clear function is used in the sequence of changing from one integration period to another. Before changing the integration period, the CC_PAUSE bit must be set to 1. Setting the CC_AUTOCLEAR bit to 1 clears the CC_OFFSET[9:0], CC_SAMPLE_CNTR[23:0], and CC_ACCUM[31:0] bit fields. The CC_AUTOCLEAR bit self-clears when the registers are reset.

Setting CC_PAUSE to 1 keeps the analog from updating the integrator, accumulator, and sample counter registers. The integrator continues to run. If an integration period ends while the CC_PAUSE bit is 1, the value that is normally written to these registers is lost and the next integration period starts automatically.

5.11.3 Dithering

The FGDITHS bit is set to 1 to enable dithering in the ADC, which keeps idle tones from being generated with a DC input value. FGDITHS is not affected by the CC_AUTOCLEAR bit. Use the FGDITHR bit to disable the dithering. The dithering feature status is available in the FGDITH_EN bit.

5.11.4 Operation Guidelines

In order to start the current gauging the host processor must first set the correct integration period (CC_ACTIVE_MODE[1:0] bits), enable the gas gauge (FGS toggle bit), and perform the calibration (CC_CAL_EN bit) to get the offset error and use that to make corrections to the measurement results. The current gauge enters normal operation automatically when calibration completes. After that, host processor can read the sample counter (CC_SAMPLE_CNTR[23:0] bits) and accumulator (CC_ACCUM[31:0] bits) results and calculate the energy accordingly.

To record the current consumption waveform,the host must use an interrupt (CC_EOC) to detect when the integration sample result is ready. The integration register CC_INTEG[13:0] always stores the result of the last measurement.

5.12.1 Real-Time Conversion Request (RT)

The real-time conversion is requested with the GPADC_START signal. Before requesting the conversion, software must enable the required channels, scalers, and current sources. In addition, software must enable the GPADC with the GPADCS bit in the TOGGLE1 register and select one or two channels for conversion with the RTSELECT_LSB, RTSELECT_ISB, and RTSELECT_MSB register bits. If more than two channels are selected for the conversion, the two lowest input numbers are converted. At the end of the conversions, the GPADC writes the conversion results into the results register (RTCH0_LSB, RTCH0_MSB, RTCH1_LSB, and RTCH1_MSB) and sets the GPADC_RT_EOC interrupt (if interrupt is unmasked).

If a GPADC_START real-time request occurs while a software-initiated conversion or BCM internal conversion is running, the ongoing conversion is aborted, the real-time conversion is started, and a new software-initiated or BCM internal conversion is rescheduled after the real-time conversion is ready.

5.12.2 Asynchronous Conversion Request (SW)

Software can also request a conversion asynchronously with respect to the GPADC_START signal. This conversion is not critical in terms of start-of-conversion positioning.

Software enables the required channels, scalers, current sources, enables the GPADC with GPADCS bit in TOGGLE1 register and selects the channel to be converted with GPSELECT_ISB register bits. The conversion is requested with SP1 bit in the CTRL_P1 register. When the conversion is ready a GPADC_SW_EOC interrupt is generated (if interrupt is unmasked) and the conversion result is available in GPCH0_LSB and GPCH0_MSB registers. A GPADC_START-initiated conversion (RT) and BCM internal conversion have higher priority than the software-initiated conversion.

If a software request occurs while a GPADC_START-initiated sequence (RT) or BCM internal conversion is running, the software request is placed on hold and the ongoing conversion continues until it completes and the converted data is stored. A GPADC_RT_EOC interrupt is then generated and sent to the processor in case of RT sequence. The digital control executes the software request when the higher priority conversion are completed. A GPADC_SW_EOC interrupt is then generated.

5.12.3 BCM Internal Conversion Request

The GPADC is automatically enabled when an internal BCM request is asserted. When this occurs, the GPADC input channel 17 is selected for a conversion. At the end of the conversion, the GPADC result is passed internally to the BCM digital control. Interrupt is not generated at the end of the BCM conversion request.

GPADC_START-initiated conversion (RT) has a higher priority than the BCM-initiated conversion.

The different ADC channels are summarized in the following table.

5.12.4 Calibration

The GPADC channels are calibrated in the production line using a two point calibration method. The channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal values (Y1 and Y2) are stored in OTP memory. The principle of the calibration is shown in Figure 5-32.

Figure 5-32 ADC Calibration Scheme

The corrected result can be calculated using the following equations.

Gain: k = 1 + ((D2 – D1) / (X2 – X1))

Offset: b = D1 – (k - 1) × X1

If the measured code is a, the corrected code a' is:

a' = (a – b) / k

Some of the GPADC channels can use the same calibration data. Table 5-3 lists the parameters X1 and X2, and the register of D1 and D2 needed in the calculation for all the channels.

5.15.1 Hot-Die Function

The HD detector monitors the temperature of the die and provides a warning to the host processor through the interrupt (HOT_DIE) when temperature reaches a critical value. The temperature threshold value is programmable with the THERM_HD_SEL[1:0] bits in the TMP_CFG register. The threshold has typically 10°C hysteresis to avoid the generation of multiple interrupts.

When an interrupt is triggered by the power-management software, immediate action to reduce the amount of power drawn from the TPS80032 device must be taken (for example, noncritical applications must be closed).

5.15.2 Thermal Shutdown

The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register.

To avoid interrupts at restart, the system cannot be restarted until the die temperature falls below the HD threshold.

The thermal shutdown monitor function is integrated to generate an immediate, unconditional TPS80032 device switch off when an overtemperature condition exists. This function must be distinguished with the early warning provided to host processor by the HD monitor function.

In the TPS80032 device, the threshold (T_J rising) of the thermal shutdown is 148°C nominal. The thermal shutdown hysteresis is 10°C in typical conditions. The reset generation is debounced. The thermal shutdown function can be masked only in the SLEEP state (the TMP_CFG_TRANS register) and in test mode.

5.15.3 Temperature Monitoring with External NTC Resistor or Diode

The GPADC_IN1 and GPADC_IN4 channels can be used to measure a temperature with an external NTC resistor. External pullup and pulldown resistors can be connected to the input to linearize the characteristics of the NTC resistor. GPADC_IN1 can be used to gate the battery charging at invalid temperatures. The temperature limits are set by external resistors.

GPADC_IN3 can be used to measure the temperature with external diode. The input channel has three selectable current sources.

5.18.1 Single-Byte Access

A write access is initiated by a first byte including the address of the device (7 most-significat bits [MSBs]) and a write command (least-significant bit [LSB]), a second byte provided the address (8 bits) of the internal register, and the third byte represents the data to be written in the internal register.

Figure 5-35 shows a write access single-byte timing diagram.

Figure 5-35 I²C Write Access Single Byte

A read access is initiated by:

• A first byte, including the address of the device (7 MSBs) and a write command (LSB)
• A second byte, providing the address (8 bits) of the internal register
• A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte representing the content of the internal register.

Figure 5-36 shows a read access single-byte timing diagram.

Figure 5-36 I²C Read Access Single Byte

5.18.2 Multiple-Byte Access to Several Adjacent Registers

A write access is initiated by:

• A first byte, including the address of the device (7 MSBs) and a write command (LSB)
• A second byte, providing the base address (8 bits) of the internal registers

The following N bytes represent the data to be written in the internal register, starting at the base address and incremented by 1 at each data byte.

Figure 5-37 shows a write access multiple-byte timing diagram.

Figure 5-37 I²C Write Access Multiple Bytes

A read access is initiated by:

• A first byte, including the address of the device (7 MSBs) and a write command (LSB)
• A second byte, providing the base address (8 bits) of the internal register
• A third byte, including again the device address (7 MSBs) and the read command (LSB)

The device replies by sending a fourth byte representing the content of the internal registers, starting at the base address and next consecutive ones.

Figure 5-38 shows a read acces multiple-byte timing diagram.

Figure 5-38 I²C Read Access Multiple Bytes