7.3.1 Power Save Mode (PSM)

The device includes a fixed on-time (t_ON) circuitry. This t_ON, in steady-state operation in PWM and PSM modes, is estimated as:

Equation 1.

To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM, the converter operates with a reduced switching frequency and with a minimum quiescent current to maintain high efficiency. The on time in PSM is also based on the same t_ON circuitry. The switching frequency in PSM is shown in Equation 1.

In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical specification table and given for a 22-µF output capacitor.

During PAUSE period in PSM (shown in Figure 4), the device does not change the PG pin state nor does it detect an UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light loads.

Figure 4. Power Save Mode Waveform Diagram