7.3.1 PWM and PSM Operation

The TPS82140 includes an on-time (t_ON) circuitry. This t_ON, in steady-state operation in PWM and PSM modes, is estimated as:

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Equation 1.

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In PWM mode, the TPS82140 operates with pulse width modulation in continuous conduction mode (CCM) with a t_ON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0MHz is achieved by this t_ON circuitry. The device operates in PWM mode as long as the output current is higher than half the inductor's ripple current estimated by Equation 2.

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Equation 2.

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To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM, the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high efficiency. PSM is also based on the t_ON circuitry. The switching frequency in PSM is estimated as:

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Equation 3.

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In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical specification table and given for a 22-µF output capacitor.

For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can reach its minimum value at high duty cycles. The output voltage remains regulated in such cases.

When V_IN decreases to typically 15% above V_OUT, the TPS82140 can't enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode.

7.3.2 Low Dropout Operation (100% Duty Cycle)

The TPS82140 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by:

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Equation 4.

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Where

R_DP = Resistance from V_IN to V_OUT, including high-side FET on-resistance and DC resistance of the inductor

V_OUT(min) = Minimum output voltage the load can accept.

7.3.3 Switch Current Limit

The switch current limit prevents the device from high inductor current and from drawing excessive current from the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition. If the inductor peak current reaches the switch current limit after a propagation delay of typically 30ns, the high-side FET is turned off and the low-side FET is turned on to ramp down the inductor current.

7.3.4 Undervoltage Lockout

To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, which shuts down the devices at voltages lower than V_UVLO with a hysteresis of 200mV.

7.3.5 Thermal Shutdown

The device goes into thermal shutdown and stops switching once the junction temperature exceeds T_JSD. Once the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.

7.4.1 Enable and Disable (EN)

The device is enabled by setting the EN pin to a logic High. Accordingly, the shutdown mode is forced if the EN pin is pulled Low with a shutdown current of typically 1.5 μA.

An internal pull-down resistor of 400kΩ is connected to the EN pin when the EN pin is Low. The pull-down resistor is disconnected when the EN pin is High.

7.4.2 Soft Startup (SS/TR)

The internal voltage clamp controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. When the EN pin is pulled high, the device starts switching after a delay of typically 55μs and the output voltage rises with a slope controlled by an external capacitor connected to the SS/TR pin. Using a very small capacitor or leaving the SS/TR pin floating provides fastest startup time.

The TPS82140 is able to start into a pre-biased output capacitor. During the pre-biased startup, both the power MOSFETs are not allowed to turn on until the internal voltage clamp sets an output voltage above the pre-bias voltage.

When the device is in shutdown, undervoltage lockout or thermal shutdown, the capacitor connected to SS/TR pin is discharged by an internal resistor. Returning from those states causes a new startup sequence.

7.4.3 Voltage Tracking (SS/TR)

The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application circuit is shown in Figure 4.

Figure 4. Output Voltage Tracking

When the SS/TR pin voltage is between 50 mV and 1.2 V, the VOUT2 tracks the VOUT1 as described in Equation 5.

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Equation 5.

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When the SS/TR pin voltage is above 1.2 V, the voltage tracking is disabled and the FB pin voltage is regulated at 0.8 V. For decreasing SS/TR pin voltage, the device doesn't sink current from the output. So the resulting decreases of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V.

Details about tracking and sequencing circuits are found in SLVA470.

7.4.4 Power Good Output (PG)

The device has a power good (PG) output. The PG pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open drain output and is specified to sink up to 2mA. The power good output requires a pull-up resistor connecting to any voltage rail less than 6V.

The PG pin goes low when the device is in shutdown or thermal shutdown. When the device is in UVLO, the PG pin is high impedance. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when it is not used. Table 1 shows the PG pin logic.