ZHCSGD2 June   2017 TPS82150

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM and PSM Operation
      2. 7.3.2 Low Dropout Operation (100% Duty Cycle)
      3. 7.3.3 Switch Current Limit
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Soft Startup (SS/TR)
      3. 7.4.3 Voltage Tracking (SS/TR)
      4. 7.4.4 Power Good Output (PG)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.8-V Output Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2 Setting the Output Voltage
          3. 8.2.1.2.3 Input and Output Capacitor Selection
          4. 8.2.1.2.4 Soft Startup Capacitor Selection
        3. 8.2.1.3 Application Performance Curves
    3. 8.3 System Examples
      1. 8.3.1 Inverting Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
        1. 11.1.2.1 使用 WEBENCH® 工具定制设计方案
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • SIL|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Voltage at pins(2) VIN –0.3 20 V
EN, SS/TR –0.3 VIN + 0.3
PG, FB –0.3 7
VOUT 0 7
Sink current PG 10 mA
Module operating temperature –40 125 °C
Storage temperature –55 125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommend Operating Conditions

MIN MAX UNIT
VIN Input voltage 3 17 V
VPG Power good pull-up resistor voltage 6 V
VOUT Output voltage 0.9 6 V
IOUT Output current 0 1 A
TJ Module operating temperature range for 100,000 hours lifetime(1) –40 110 °C
(1) The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where high power dissipation is present, the maximum operating temperature or maximum output current must be derated. For applications where the module operates continuously at 125 °C temperature, the maximum lifetime is reduced to 50,000 hours.

6.4 Thermal Information

THERMAL METRIC(1) TPS82150 UNIT
8-Pin SIL
JEDEC 51-5 EVM
RθJA Junction-to-ambient thermal resistance 58.2 46.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.4 9.4 °C/W
RθJB Junction-to-board thermal resistance 14.4 14.4 °C/W
ψJT Junction-to-top characterization parameter 0.9 0.9 °C/W
ψJB Junction-to-board characterization parameter 14.2 14.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 21.3 21.3 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Theta-JA can be improved with a custom PCB design containing thermal vias where possible.

6.5 Electrical Characteristics

TJ = -40°C to 125°C and VIN = 3.0V to 17V. Typical values are at TJ = 25°C and VIN = 12V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current into VIN No load, device not switching 20 35 µA
ISD Shutdown current into VIN EN = Low 1.5 7.4 µA
VUVLO Under voltage lock out threshold VIN falling 2.6 2.7 2.8 V
VIN rising 2.8 2.9 3.0 V
TJSD Thermal shutdown threshold TJ rising 160 °C
TJ falling 140 °C
LOGIC INTERFACE (EN)
VIH High-level input voltage 0.9 0.65 V
VIL Low-level input voltage 0.45 0.3 V
Ilkg(EN) Input leakage current into EN pin EN = High 0.01 1 µA
CONTROL (SS/TR, PG)
ISS/TR SS/TR pin source current 2.1 2.5 2.8 µA
VPG Power good threshold VOUT rising, referenced to VOUT nominal 92% 95% 99%
VOUT falling, referenced to VOUT nominal 87% 90% 94%
VPG,OL Power good low-level voltage Isink = 2mA 0.1 0.3 V
Ilkg(PG) Input leakage current into PG pin VPG = 1.8V 1 400 nA
OUTPUT
VFB Feedback regulation voltage PWM mode 785 800 815 mV
TJ = 0°C to 85°C 788 800 812
PSM COUT = 22µF 785 800 823
COUT = 2x22µF, TJ = 0°C to 85°C 788 800 815
Ilkg(FB) Feedback input leakage current VFB = 0.8V 1 100 nA
Line regulation IOUT = 1A, VOUT = 1.8V 0.002 %/V
Load regulation IOUT = 0.5A to 1A, VOUT = 1.8V 0.12 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance ISW = 500mA, VIN ≥ 6V 90 170 mΩ
ISW = 500mA, VIN = 3V 120
Low-side FET on-resistance ISW = 500mA, VIN ≥ 6V 40 70
ISW = 500mA, VIN = 3V 50
RDP Dropout resistance 100% mode, VIN ≥ 6V 125 mΩ
100% mode, VIN = 3V 160
ILIMF High-side FET switch current limit VIN = 6V, TJ = 25°C 1.7 2.2 2.7 A
fSW PWM switching frequency IOUT = 1A, VOUT = 1.8V 2.0 MHz

6.6 Typical Characteristics

TPS82150 D014_SLVSCY5_TPS82130.gif
Figure 1. Dropout Resistance
TPS82150 D026_SLVSCY5_TPS82130.gif
Figure 3. Shutdown Current
TPS82150 D025_SLVSCY5_TPS82130.gif
Figure 2. Quiescent Current
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