8.3.11 PWM (UVLO and Enable)

If PWM dimming or ON/OFF control is not needed in the application, tie the PWM pin to the VCC pin.

Use the PWM pin for PWM dimming. Use a signal above 1 V (typical) and below 900 mV (typical) when measured at the PWM pin. Standard PWM frequency ranges can also be used (100 Hz to 2 kHz). Higher frequencies can cause the delays from PWM to gate turn ON and turn OFF to limit the achievable duty cycle.

For example, the PWM to gate delay (turn on + turn off ≈ 100 ns) and the time to slew the switchnode up and down (approximately 100 ns) total approximately 200 ns.

For example, if a 10 kHz PWM frequency is desired having a period of 100 μs, the minimum duty cycle is 200 ns/100 μs = 0.2%. This is sometimes referred to as 500:1 dimming. As the PWM signal width becomes smaller, the converter ON and OFF time are eventually controlled by the PWM input signal directly. For example, if the PWM ON-time is shorter than the converter natural demanded ON-time, the PWM signal itself becomes the control signal for the high-side switch. The PWM pin activates a weak pulldown, as shown in Figure 25. Because the PWM pin also controls UVLO (undervoltage lockout and device enable), when pulled low it is necessary to ensure the output is 100% OFF. The high-side FET driver has a small leakage path to the output. Although very small (<<100 μA), the LEDs can glow if the current was not eliminated. The device activates the 100-μA (typical) pulldown circuitry and it remains ON while PWM is low. This activation ensures that the LED emits no light.