ZHCSLI9A December   2021  – June 2022 TPS92623-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply (SUPPLY)
        1. 7.3.1.1 Power-On Reset (POR)
        2. 7.3.1.2 Suppply Current in Fault Mode
      2. 7.3.2  Enable and Shutdown
      3. 7.3.3  Constant-Current Output and Setting (INx)
      4. 7.3.4  Thermal Sharing Resistor (OUTx and RESx)
      5. 7.3.5  PWM Control (PWMx)
      6. 7.3.6  Supply Control
      7. 7.3.7  Diagnostics
        1. 7.3.7.1 LED Short-to-GND Detection
        2. 7.3.7.2 LED Open-Circuit Detection
        3. 7.3.7.3 LED Open-Circuit Detection Enable (DIAGEN)
        4. 7.3.7.4 Overtemperature Protection
        5. 7.3.7.5 Low Dropout Operation
      8. 7.3.8  FAULT Bus Output with One-Fails-All-Fail
      9. 7.3.9  FAULT Table
      10. 7.3.10 LED Fault Summary
      11. 7.3.11 IO Pins Inner Connection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY) < V(POR_rising)
      2. 7.4.2 Normal Operation V(SUPPLY) ≥ 4.5 V
      3. 7.4.3 Low-Voltage Dropout Operation
      4. 7.4.4 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 BCM Controlled Rear Lamp With One-Fails-All-Fail Setup
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Independent PWM Controlled Rear Lamp By MCU
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.5 Electrical Characteristics

V(SUPPLY) = 5 V to 40 V, V(EN) = 5V, TJ = –40°C to +150°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(POR_rising) Supply voltage POR rising threshold 3.6 4.0 V
V(POR_falling) Supply voltage POR falling threshold 3.0 3.4 V
I(Quiescent) Device standby ground current PWM = HIGH 1.6 2.5 mA
I(FAULT) Device supply current in fault mode PWM = HIGH, FAULT externally pulled LOW 0.21 0.350 0.45 mA
LOGIC INPUTS (DIAGEN, PWM)
VIL(DIAGEN) Input logic-low voltage, DIAGEN 1.045 1.1 1.155 V
VIH(DIAGEN) Input logic-high voltage, DIAGEN 1.14 1.2 1.26 V
VIL(PWM) Input logic-low voltage, PWM 1.045 1.1 1.155 V
VIH(PWM) Input logic-high voltage, PWM 1.14 1.2 1.26 V
CONSTANT-CURRENT DRIVER
I(OUTx_Tot) Device output-current for each channel 100% duty cycle 5 150 mA
V(CS_REG) Sense-resistor regulation voltage TA = –40°C to +125°C 144 150 156 mV
ALL ΔV(CS_c2c) Channel to channel mismatch ΔV(CS_c2c) = 1 – V(CS_REGx)/Vavg(CS_REG) –3 +3 %
ALL ΔV(CS_d2d) Device to device mismatch ΔV(CS_d2d) = 1 – Vavg(CS_REG)/Vnom(CS_REG) –4 +4 %
R(CS_REG) Sense-resistor range 0.96 31.2 Ω
V(DROPOUT) Voltage dropout from INx to OUTx, RESx open current setting of 100 mA 200 400 mV
current setting of 150 mA 300 600
Voltage dropout from INx to RESx, OUTx open current setting of 100 mA 280 600 mV
current setting of 150 mA 400 900
I(RESx) Ratio of RESx current to total current I(RESx)/I(OUTx_Tot), V(INx) – V(RESx) > 1 V 95 %
DIAGNOSTICS
V(OPEN_th_rising) LED open rising threshold, V(IN) – V(OUT) 180 300 420 mV
V(OPEN_th_falling) LED open falling threshold, V(IN) – V(OUT) 450 mV
V(SG_th_rising) Channel output short-to-ground rising threshold 1.14 1.2 1.26 V
V(SG_th_falling) Channel output short-to-ground falling threshold 0.855 0.9 0.945 V
I(Retry_OUTx) Channel output V(OUT) short-to-ground retry current 0.64 1.08 1.528 mA
I(Retry_RESx) Channel output V(OUT) short-to-ground retry current 0.64 1.08 1.528 mA
FAULT
VIL(FAULT) Logic input low threshold 0.7 V
VIH(FAULT) Logic input high threshold 2 V
t(FAULT_rising) Fault detection rising edge deglitch time 10 µs
t(FAULT_falling) Fault detection falling edge deglitch time 20 µs
I(FAULT_pulldown) FAULT internal pulldown current V(FAULT) = 0.4 V 2 3 4 mA
I(FAULT_pullup) FAULT internal pullup current 6 10 14 µA
I(FAULT_leakage) FAULT leakage current V(FAULT) = 20 V 0.01 2 µA
TIMING
t(PWM_delay_rising) PWM rising edge delay to 10% of output current, t1 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 Ω and R(RESx) = 56 Ω 3 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 Ω and R(RESx) = 56 Ω 3 µs
t(PWM_delay_falling) PWM falling edge delay to 90% of output current, t2 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 Ω and R(RESx) = 56 Ω 3.8 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 Ω and R(RESx) = 56 Ω 3.8 µs
t(Current_rising) Output current rising from 10% to 90%, t3 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 Ω and R(RESx) = 56 Ω 2 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 Ω and R(RESx) = 56 Ω 1 µs
t(Current_falling) Output current falling from 90% to 10%, t4 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 Ω and R(RESx) = 56 Ω 5 µs
V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 Ω and R(RESx) = 56 Ω 0.2 µs
t(STARTUP) SUPPLY rising edge to 10% output current, t5 as shown in Figure 7-1 V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 Ω and R(RESx) = 56 Ω 85 µs
t(OPEN_deg) LED-open fault detection deglitch time, t6 as shown in Figure 7-4 125 µs
t(SG_deg) Output short-to-ground detection deglitch time, t7 as shown in Figure 7-3 125 µs
t(Recover_deg) Open and Short fault recovery deglitch time, t8 as shown in Figure 7-3 and Figure 7-4  125 µs
t(FAULT_recovery) Fault recovery delay time, t9 as shown in Figure 7-3 and Figure 7-4 50 µs
t(TSD_deg) Thermal over temperature deglitch time 50 µs
THERMAL PROTECTION
T(TSD) Thermal shutdown junction temperature threshold 157 172 187 °C
T(TSD_HYS) Thermal shutdown junction temperature hysteresis 15 °C
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