ZHCSP77A December 2021 – March 2022 TPS92624-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| t(PWM_delay_rising) | PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t1 as shown in Figure 7-1 | 3 | 6 | µs | |
| PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t1 as shown in Figure 7-1 | 3 | 6 | µs | ||
| PWM rising edge delay, VIH(PWM) voltage to 10% of output current closed loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t1 as shown in Figure 7-1 | 3 | 6 | µs | ||
| t(PWM_delay_falling) | PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t3 as shown in Figure 7-1 | 1.2 | 2.4 | 3.6 | µs |
| PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t3 as shown in Figure 7-1 | 1.6 | 2.6 | 4.2 | µs | |
| PWM falling edge delay, VIL(PWM) voltage to 90% of output current open loop when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t3 as shown in Figure 7-1 | 1.6 | 2.6 | 4.2 | µs | |
| t(Current_rising) | Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t2 as shown in Figure 7-1 | 2 | 5 | µs | |
| Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t2 as shown in Figure 7-1 | 3 | 6 | µs | ||
| Output current rising from 10% to 90% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t2 as shown in Figure 7-1 | 3 | 6 | µs | ||
| t(Current_falling) | Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t4 as shown in Figure 7-1 | 5 | 7 | µs | |
| Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 50 mV, R(SNSx) = 1 Ω and R(RESx) = 110 Ω, t4 as shown in Figure 7-1 | 1 | 2 | µs | ||
| Output current falling from 90% to 10% when V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 50 mV, R(SNSx) = 10 Ω and R(RESx) = 27 Ω, t4 as shown in Figure 7-1 | 1 | 2 | µs | ||
| t(STARTUP) | SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 0.665 Ω and R(RESx) = 56 Ω, t5 as shown in Figure 7-1 | 55 | 100 | µs | |
| SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 10 Ω and R(RESx) = 110 Ω, t5 as shown in Figure 7-1 | 55 | 100 | µs | ||
| SUPPLY rising edge to 10% output current when C(IREF) = C(ICTRL)= 10 pF, V(OUT) = 6 V, V(CS_REG) = 100 mV, R(SNSx) = 1 Ω and R(RESx) = 27 Ω, t5 as shown in Figure 7-1 | 55 | 100 | µs | ||
| t(OPEN_deg) | LED-open fault-deglitch time, t6 as shown in Figure 7-4 | 75 | 125 | 199 | µs |
| t(SG_deg) | Output short-to-ground detection deglitch time, t7 as shown in Figure 7-3 | 75 | 125 | 199 | µs |
| t(Recover_deg) | Open and Short fault recovery deglitch time, t8 as shown in Figure 7-4 and Figure 7-3 | 75 | 125 | 199 | µs |
| t(FAULT_deg) | Fault pin digital deglitch time | 7 | 10 | 13 | µs |
| t(FAULT_recovery) | Fault recovery delay time, t9 as shown in Figure 7-4 and Figure 7-3 | 30 | 50 | 84 | µs |
| t(TSD_deg) | Thermal over temperature deglitch time | 30 | 50 | 84 | µs |