10.1 Layout Guidelines

The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI within the circuit.

Discontinuous currents are the most likely to generate EMI, therefore take care when routing these paths. The main path for discontinuous current in the TPS92640 and TPS92641 buck converters contain the input capacitor (C_IN), the low side MOSFET (Q_LS), and the high side MOSFET (Q_HS). This loop should be kept as small as possible and the connections between all three components should be short and thick to minimize parasitic inductance. In particular, the switch node (where L, Q_LS and Q_HS connect) should be just large enough to connect the components without excessive heating from the current it carries. The current sense trace (CS pin) should be run along with a ground plane or have differential traces run for CS and ground.

In some applications, the LED or LED array can be far away (several inches or more) from the circuit, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor.

10.2 Layout Example

Figure 26. Layout Recommendation

10.3 EMI and Noise Considerations

In synchronous rectifier, the high speed gate drive signals can generate significant conducted and radiated EMI. This noise can couple with high impedance nodes of the IC and result in undesirable operation. A small (4 Ω to 10 Ω) resistors, R_HG and R_LG, in series with the gate drive signals are recommended to slow the slew-rate of the SW node and reduce the noise signature. They also improve the robustness of the circuit by reducing the noise coupling in to sensitive nodes such as UDIM, CS, RON and IADJ.

In other to further reduce EMI signature, good PCB layout techniques must be implemented. The loop area between the synchronous NFET, inductor and output capacitor should be minimized to reduce radiated EMI due to switching action. The trace lengths of high impedance nodes (UDIM, CS, RON and IADJ) should be minimized and shielded from switching noise. The parasitic capacitance between switching node and ground node should be minimized to reduce common mode noise. Other common layout techniques such as star ground and noise suppression using local bypass capacitors should be followed to maximize noise rejection and minimize EMI within the circuit.